Interview Questions.

Q1. Explain how logical gates are managed by means of Boolean logic?

Ans: In Boolean algebra, the proper kingdom is denoted by the primary, referred as good judgment one or good judgment high. While, the fake kingdom is represented through the number zero, called common sense zero or good judgment low.  And in the virtual electronic, the common sense high is denoted through the presence of a voltage capability.

Q2. Mention what are the exceptional gates where Boolean common sense are relevant?

Ans: 

NOT Gate:It has one out enter and one output. For example, if the price of A= zero then the Value of B=1 and vice versa

AND Gate:It has one output due to the mixture of two output. For example, if the price of A and B= 1 then price of Q need to be 1

OR Gate:Either of the price will show the identical output. For example, if the value of A is 1 or B is 0 then cost of Q is 1

These are the primary three varieties of gates wherein Boolean common sense paintings, other than these, different gates which can be purposeful works with the aggregate of these three fundamental gates, they may be XNOR gate, NAND gate, Nor gate and XOR gate.

Q3. Explain how binary range can give a signal or convert into a digital sign?

Ans: Binary range consists of either zero or 1, in easy words #1 represents the ON state and quantity 0 represents OFF country. These binary numbers can integrate billion of machines into one machines or circuit and function the ones machines by means of acting mathematics calculations and sorting operations.

Q4. Mention what is the difference between the TTL chips and CMOS chips?

Ans: 

                               TTL Chips                              CMOS Chips

·          TTL chips for transistor transistor common sense. It uses two Bi-polar Junction Transistors inside the layout of each logic gate

·          TTL chips can consist of a widespread quantity of elements like resistors

·          TTLS chip consumes lot greater power in particular at relaxation. A unmarried gate in TTL chip consumes approximately mW of electricity

·          TTL chips can be used in computer systems

·           CMOS stands for Complementary Metal Oxide Semi-conductor. It is likewise an included chip however used area impact transistors in the design

·          CMOS has more density for common sense gates. In a CMOS chip, single good judgment gate can contain of as little as two FETs

·          CMOS chips eat less energy. A unmarried CMOS chip devour approximately 10nW of power

·          CMOS chip is used in Mobile phones

 

Q5. Explain what is a sequential circuit?

Ans: A sequential circuit is a circuit which is created via logic gates such that the desired good judgment at the output depends now not simplest at the modern-day input logic conditions, however also on the sequences past inputs and outputs.

Q6. Explain how Verilog is distinct to everyday programming language?

Ans: Verilog can be one-of-a-kind to regular programming language in following components

Simulation time idea

Multiple threads

Basic circuit standards like primitive gates and community connections

Q7. Explain what is Verilog?

Ans: Verilog is an HDL (Hardware Description Language) for describing electronic circuits and systems.  In Verilog, circuit components are organized internal a Module.  It carries each behavioral and structural statements.  Structural statements signify circuit additives like common sense gates, counters and micro-processors. Behavioral statements constitute programming aspects like loops, if-then statements and stimulus vectors.

Q8. In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

Q9. Mention what are the two styles of procedural blocks in Verilog?

Ans: The two forms of procedural blocks in Verilog are

Initial:Initial blocks runs handiest once at time 0

Always:This block loop to execute over and once more and executes always, because the call shows

Q10. Explain why present VLSI circuits use MOSFETs rather than BJTs?

Ans: In contrast to BJT, MOSFETS may be made very compact as they occupy very small silicon region on IC chip and additionally in time period of manufacturing they're relatively simple. Moreover, digital and memory ICs may be hired with circuits that use only MOSFETs, i.E., diodes, resistors, and so forth.

Q11. Mention what are three regions of operation of MOSFET and how are they used?

Ans: MOSFET has 3 regions of operations

Cut-off location

Triode location

Saturation region

The triode and cut-off vicinity are used to function as a transfer, even as, saturation place is used to operate as an amplifier.

Q12. Explain what's the depletion vicinity?

Ans: When positive voltage is transmitted across Gate, it causes the free holes (superb fee) to be pushed returned or repelled from the area of the substrate under the Gate. When those holes are driven down the substrate, they depart behind a carrier depletion place.

Q13. Explain why is the range of gate inputs to CMOS gates usually restricted to 4?

Ans: Higher the number of stacks, slower the gate could be.  In NOR and NAND gates the range of gates present within the stack is commonly alike as the range of inputs plus one. So enter are restricted to 4.

Q14. Explain what's multiplexer?

Ans: A multiplexer is a combination circuit which selects one of the many input indicators and direct to the most effective output.

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Q15. Explain what's SCR (Silicon Controlled Rectifier)?

Ans: SCR is a four layered solid state tool which controls current drift.  It is a type of rectifier this is managed by a logical gate sign. It is a 4 layered, three-terminal device.

Q16. Explain what is Slack?

Ans: Slack is referred as a time postpone difference from the predicted put off to the actual postpone in a specific course. Slack can be negative or advantageous.

Q17. Explain what's the usage of defpararm?

Ans: With the key-word defparam, parameter values may be configured in any module example within the layout.

Q18. What are the steps required to solve setup and Hold violations in VLSI?

Ans: There are few steps that must be accomplished to solved the setup and keep violations in VLSI. The steps are as follows:

- The optimization and restructuring of the logic between the flops are carried manner. This manner the logics are combined and it helps in solving this hassle.

- There is manner to modify the flip-flops that offer lesser setup delay and provide faster services to setup a device.

Modifying the launch-flop to have a higher keep at the clock pin, which gives CK->Q that makes the launch-flop to be speedy and facilitates in solving the setup violations.

- The community of the clock can be changed to reduce the put off or slowing down of the clock that captures the action of the turn-flop.

- There may be added put off/buffer that lets in less delay to the feature this is used.

Q19. What are the extraordinary ways wherein antenna violation may be averted?

Ans: Antenna violation happens in the course of the manner of plasma etching in which the charges producing from one metallic strip to any other gets accumlated at a unmarried region. The longer the strip the more the charges receives accrued. The prevention may be carried out by means of following approach:

- Creating a running the metallic line, that includes atleast one metallic above the blanketed layer.

- There is a requirement to jog the metallic that is above the metallic getting the etching impact. This is because of the reality that if a metal receives the etching then the alternative metal receives disconnected if the prevention measures aren't taken.

- There is a manner to save you it with the aid of including the opposite Diodes on the gates which can be used within the circuits.

Q20. What is the feature of tie-high and tie-low cells?

Ans: Tie-high and tie-low are used to attach the transistors of the gate via the usage of both the electricity or the floor. The gates are linked using the energy or ground then it may be became on and off due to the electricity leap from the ground. The cells are used to forestall the bouncing and smooth from of the modern from one cellular to some other. These cells are required Vdd that connects to the tie-high cellular as there is a energy deliver that is high and tie-low gets connected to Vss. This connection gets hooked up and the transistors feature properly with out the need of any ground jump occurring in any cell.

Q21. What is the main function of metastability in VSDL?

Ans: Metastability is an unknown nation this is given as neither one or zero. It is used in designing the device that violates the setup or hollow time requirements. The setup time requirement need the statistics to be strong earlier than the clock-side and the hold time calls for the data to be solid after the clock area has passed. There are potential violation that may result in setup and hold violations as well. The statistics that is produced in that is definitely asynchronous and clocked synchronous. This offer a manner to setup the country via which it may be known that the violations which are occuring inside the device and a right design can be supplied by way of the use of several other functions.

Q22. What are the steps concerned in stopping the metastability?

Ans: Metastability is the unknown state and it prevents the violations the usage of the following steps:

1. Proper synchronizers are used that may be  degree or 3 stage every time the information comes from the asynchronous domain. This facilitates in improving the metastable country occasion.

2. The synchronizers are utilized in between move-clocking domain names. This reduces the metastability by doing away with the put off that is because of the statistics element which are coming and taking time to get eliminated from the surface of metallic.

3. Use of faster flip-flops that permit the transaction to be greater quicker and it gets rid of the postpone time among the one issue to every other factor. It uses a narrower metastable window that makes the delay happen but quicker flip-flops assist in making the method faster and reduce the time delay as well.

Q23. What are the distinct design constraints arise inside the Synthesis segment?

Ans: The steps which are involved wherein the layout constraint takes place are:

1. First the introduction of the clock with the frequency and the duty cycle gets created. This clock facilitates in preserving the go with the flow and synchronizing various gadgets which might be used.

2. Define the transition time according the requirement on the input ports.

3. The load values are specific for the output ports which can be mapped with the input ports.

Four. Setting of the postpone values for each the enter and output ports. The postpone consists of the input and output delay.

Five. Specify the case-settings to document the right time which are matched with the precise paths.

6. The clock uncertainty values are setup and keep to reveal the violations which can be occurring.

Q24. What are the distinctive varieties of skews utilized in VLSI?

Ans: There are three kinds of skew which can be used in VLSI. The skew are utilized in clock to reduce the put off or to understand the technique for this reason. The skew are as follows:

Local skew:

This comprise the difference among the launching flip-flop and the vacation spot turn-flop. This defines a time route between the two.

Global skew:

Defines the distinction between the earliest issue accomplishing the flip go with the flow and the the modern-day arriving at the flip flow with the equal clock area. In this delays are not measured and the clock is supplied the equal.

Useful skew:

Defines the delay in shooting a flip flop paths that facilitates in putting in the surroundings with unique requirement for the launch and capture of the timing route. The keep requirement in this situation must be met for the design cause.

Q25. What are the changes which might be provided to fulfill design electricity targets?

Ans: To meet the design electricity goal there ought to be a manner to layout with Multi-VDD designs, this region calls for high overall performance, and also the excessive VDD that requires low-performance. This is used to create the voltage institution that permit an appropriate stage-shifter to shift and placed in go-voltage domains. There is a layout with the multiple threshold voltages that require high performance when the Vt turns into low. This have lots of current leakage that makes the Vt cell to lower the performance. The reduction can be accomplished in the leakage strength as the clock on this devour extra power, so placing of an most desirable clock controls the module and permit it to take delivery of extra energy. Clock tree allow the switching to take region when the clock buffers are utilized by the clock gating cells and decrease the switching by the energy reduction.

Q26. What are the different measures that are required to reap the design for better yield?

Ans: To acquire better yeild then there should be reduction in maufacturability flaws. The circuit perfomance has to be high that reduces the parametric yield. This reduction is due to system versions The measures that may be taken are:

- Creation of powerful runset files that includes spacing and shorting policies. This also consists of all the permissions that has to accept to the user.

- Check the regions wherein the layout is having lithographic troubles, that consists of sharp cuts.

- Use of redundant vias to reduce the breakage of the modern and the barrier.

- Optimal placing of the de-coupling capacitances can be done in order that there's a discount in energy-surges.

Q27. What is the distinction among the mealy and moore nation machine?

Ans:

- Moore version includes the device which have an access movement and the output relies upon handiest at the state of the machine, whereas mealy model only uses Input Actions and the output depends at the country and also on the previous inputs which might be supplied for the duration of the program.

- Moore models are used to layout the hardware systems, whereas each hardware and software program structures can be designed using the mealy version.

- Mealy gadget's output rely on the country and input, while the output of the moore system relies upon only at the kingdom as the application is written within the state handiest.

- Mealy gadget is having the output by way of the combination of both input and the country and the change the nation of state variables also have a few postpone whilst the exchange inside the signal takes area, whereas in Moore machine does not have system faults and its ouput relies handiest on states no longer at the enter sign level.

Q28. What is the distinction among Synchronous and Asynchronous reset?

Ans:

- Synchronous reset is the logic so as to synthesize to smaller turn-flops. In this the clock works as a filter offering the small reset system faults however the glitches arise at the energetic clock edge, whereas the asynchronous reset is likewise called reset launch or reset elimination. The dressmaker is responsible of brought the reset to the facts paths.

- The synchronous reset is used for all of the varieties of design which are used to clear out the logic system defects supplied between the clocks. Whereas, the circuit can be reset without or with the clock gift.

- Synchronous reset would not permit the synthesis tool for use easily and it distinguishes the reset signal from other facts signal. The launch of the reset can arise simplest whilst the clock is having its preliminary length. If the discharge occurs near the clock part then the flip-flops can be metastable.

Q29. What are the exceptional layout strategies required to create a Layout for Digital Circuits?

Ans: The specific design strategies to create the Layout for digital circuits are as follows:

- Digital layout consists of the standard cells and represent the height that is required for the layout. The format relies upon on the dimensions of the transistor. It also includes the specification for Vdd and GND steel paths that needs to be maintained uniformly.

- Use of metallic in one route only to use the metallic at once. The steel can be used and displayed in any course.

- Placing of the substrate that location where it shows all the empty spaces of the layout wherein there's resistances.

- Use of fingered transistors allows the layout to be more easy and it is straightforward to preserve a symmetry as well.

Q30. Write a software to provide an explanation for the comparator?

Ans: To make a comparator there may be a demand to use multiplexer this is having one input and plenty of outputs. This lets in the choosing of the maximum numbers which can be required to design the comparator. The implementation of the 2 bit comparator can be carried out the use of the law of tigotomy that states that A > B, A < B, A = B (Law of trigotomy). The comparator can be implemented using:

combinational logic circuits or multiplexers that uses the HDL language to write the schematic at RTL and gate level.

Behavioral model of comparator represented like:

module comp0 (y1,y2,y3,a,b);

input [1:0] a,b;

output y1,y2,y3;

wire y1,y2,y3;

assign y1= (a >b)? 1:zero;

assign y2= (b >a)? 1:0;

assign y3= (a==b)? 1:0;

endmodule

Q31. What is the characteristic of chain reordering?

Ans: The optimization technique this is used makes it hard for the chain ordering machine to path because of the congestion caused by the placement of the cells. There are tool to be had that automate the reordering of the chain to lessen the congestion that is produced at the primary degree. It will increase the problem of the chain gadget and this additionally permit the overcoming of the buffers that have to be inserted into the experiment direction. The growth of the hold time inside the chain reordering can reason awesome amount of delay. Chain reordering allows the cell to be come within the ordered layout even as the usage of the special clock domain names. It is used to lessen the time delay because of random technology of the detail and the location of it.

 Q32. What are the steps worried in designing an most beneficial pad ring?

Ans:

- To make the layout for an top-quality pad ring there's a requirement for the corner-pads that comes throughout all of the corners of the pad-ring. It is used to offer electricity continuity and hold the resistance low.

- It calls for the pad ring that is to fulfil the strength domains this is not unusual for all of the floor across all of the domain names.

- It requires the pad ring to comprise simultaneous switching noise system that region the transfer mobile pads in go energy domains for specific pad length.

- Drive electricity is been seen to check the contemporary requirements and the timings to make the electricity pads.

- Choose a no-connection pad this is used to fill the pad-frame whilst there's no requirement for the inputs to be given. This consumes much less energy while there's no enter given at a selected time.

- Checking of the oscillators pads take location that makes use of the synchronous circuits to make the clock records synchronize with the present one.

Q33. What is the feature of enhancement mode transistor?

Ans: The enhancement mode transistors also are known as as area effect transistors as they rely on the electrical filed to control the shape and conductivity of the channel. This includes one sort of price carrier in a semiconductor cloth environment. This additionally makes use of the unipolar transistors to differentiate themselves with the single-service type operation transistors that includes the bipolar junction transistor. The uses of field effect transistor is to bodily implementation of the semiconductor substances this is compared with the bipolar transistors. It offers with the majority of the rate provider devices. The devices that consists of active channels to make the charge companies pass thru. It includes the idea of drain and the source.

Q34. What is the motive of having Depletion mode Device?

Ans: Depletion modes are used in MOSFET it is a tool that remains ON at 0 gate-source voltage. This tool includes load resistors that are used inside the logic circuits. This sorts are utilized in N-type depletion-load devices that allow the brink voltages to be taken and use of -3 V to +3V is executed. The drain is extra superb in this assessment of PMOS in which the polarities gets reversed. The mode is normally determined by using the sign of threshold voltage for N-type channel. Depletion mode is the superb one and used in many technologies to symbolize the actual good judgment circuit. It defines the logic circle of relatives this is dependent on the silicon VLSI. This includes pull-down switches and masses for pull-ups.

Q35. What is the distinction among NMOS and PMOS technologies?

Ans:

- PMOS includes steel oxide semiconductor that is made on the n-type substrates and includes energetic careers named as holes. These holes are used for migration purpose of the charges among the p-type and the drain. Whereas, NMOS includes the metal oxide semiconductor and they're made on p-type substrates. It includes electrons as their carriers and migration occurs among the n-type source and drain.

- On applying the excessive voltage at the common sense gates NMOS can be carried out and could get activated, whereas PMOS require low voltage to be activated.

- NMOS are quicker than PMOS as the vendors that NMOS makes use of are electrons that travels faster than holes. The speed is twice as fast as holes.

- PMOS are more proof against noice than NMOS.

 Q36. What is the difference among CMOS and Bipolar technologies?

Ans:

- CMOS era lets in the electricity dissipation to be low and it offers extra electricity output, while bipolar takes lots of electricity to run the machine and the ciricutary require lots of strength to get activated.

- CMOS era provides excessive enter impedance this is low force present day that allow extra modern to be flown within the cirucit and maintain the circuit in a terrific role, whereas it provides excessive drive present day manner extra input impedance.

- CMOS technology affords scalable threshold voltage greater in contrast to the Bipolar generation that provides low threshold voltage.

- CMOS generation offers high noise margin, packing density while Bipolory era permits to have low noise margin so that to lessen the high volues and deliver low packing density of the components.

Q37. What are the unique class of the timing control?

Ans: There are distinctive category wherein the timing manage information is divided and they are:

1. Delay based timing manage: this is based on timing control that allows to control the thing such that the postpone can be notified and anywhere it's miles required it is able to receive. The delays which are based totally on this are as:

- Regular put off control: that controls the postpone at the ordinary basis.

- Intra-venture delay control: that controls the internal delays.

- Zero postpone manage

2. Events based totally timing control: this is primarily based at the occasions which might be done when an occasion happens or a trigger is ready on an occasion that takes vicinity. It consists of

- Regular event manage

- Named event manage

- Event OR manage

3. Level sensitive timing control: that is primarily based at the stages which might be given like 0 level or 1 degree that is being given or shown and the records is being modified according the stages which are being set. When a stage changes the timing control additionally changes.