Interview Questions.

Q1. What Is Difference Between Verilog Full Case And Parallel Case?

Ans: A "full" case assertion is a case declaration wherein all feasible case-expression binary styles can be matched to a case item or to a case default. If a case statement does no longer consist of a case default and if it is viable to find a binary case expression that does not in shape any of the defined case gadgets, the case assertion isn't "full."

A "parallel" case statement is a case assertion in which it's miles most effective possible to suit a case expression to 1 and most effective one case item. If it is feasible to find a case expression that might match multiple case object, the matching case objects are referred to as "overlapping" case items and the case declaration is not "parallel."

Q2. What Is Pli?Why Is It Used?

Ans: Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog applications with programs written in C language. It also offers mechanism to access inner databases of the simulator from the C software.

PLI is used for implementing system calls which would were hard to do otherwise (or impossible) the usage of Verilog syntax. Or, in other phrases, you could take gain of both the paradigms - parallel and hardware associated capabilities of Verilog and sequential waft of C - using PLI.

Q3. Difference Between $monitor,$show & $strobe?

Ans: These instructions have the identical syntax, and show textual content at the display at some point of simulation. They are a lot less convenient than waveform show gear like cwaves?. $show and $strobe show as soon as each time they're carried out, while $display presentations whenever one of its parameters changes.

The difference among $show and $strobe is that $strobe displays the parameters at the very stop of the modern simulation time unit in preference to precisely where it's miles performed. The layout string is like that during C/C++, and may incorporate format characters. Format characters include %d (decimal), %h (hexadecimal), %b (binary), %c (person), %s (string) and %t (time), %m (hierarchy level). %5d, %5b and so forth. Might give exactly 5 spaces for the wide variety as opposed to the gap wished. Append b, h, o to the assignment call to exchange default format to binary, octal or hexadecimal.

Q4. Variable And Signal Which Will Be Updated First?

Ans: Signals

Q5. What Is Sensitivity List?

Ans: The sensitivity list suggests that once a exchange occurs to any person of factors within the listing change, start…give up announcement internal that constantly block gets done.

Q6. In A Pure Combinational Circuit Is It Necessary To Mention All The Inputs In Sensitivity Disk? If Yes, Why?

Ans: Yes in a pure combinational circuit is it vital to say all of the inputs in sensitivity disk different sensible it's going to bring about pre and publish synthesis mismatch.

Q7. Write A Verilog Code To Swap Contents Of Two Registers With And Without A Temporary Register?

Ans: With temp reg ;

always @ (posedge clock)

begin

temp=b;

b=a;

a=temp;

stop

Without temp reg;

always @ (posedge clock)

start

a <= b;

b <= a;

quit

Q8. Difference Between Task And Function?

Ans: Function: 

A function is not able to enable a assignment but features can allow other features.

A feature will perform its required responsibility in zero simulation time. ( The software time will no longer be incremented all through the feature habitual)

Within a characteristic, no occasion, postpone or timing manipulate statements are accepted

In the invocation of a characteristic their need to be as a minimum one argument to be surpassed.

Functions will most effective return a unmarried cost and can not use either output or inout statements.

Tasks: 

Tasks are able to enabling a characteristic as well as permitting different variations of a Task

Tasks additionally run with a 0 simulation but they can if required be executed in a non zero simulation time.

Tasks are allowed to incorporate any of these statements.

A mission is permitted to use zero or greater arguments which might be of type output, input or inout.

A Task is not able to return a price however has the facility to pass a couple of values thru the output and inout statements .

Q9. Difference Between Inter Statement And Intra Statement Delay?

Ans: //outline sign in variables

reg a, b, c;

//intra project delays

preliminary

start

a = zero; c = 0;

b = #five a + c; //Take fee of a and c on the time=zero, evaluate

//a + c and then wait five time gadgets to assign value

//to b.

Give up

//Equivalent method with temporary variables and normal delay manage

preliminary

begin

a = zero; c = 0;

temp_ac = a + c;

#five b = temp_ac; //Take cost of a + c on the modern time and

//store it in a transient variable. Even although a and c

//would possibly alternate among zero and five,

//the price assigned to b at time five is unaffected.

Give up

Syntax:

$show (“format_string”, par_1, par_2, ... );

$strobe (“format_string”, par_1, par_2, ... );

$reveal (“format_string”, par_1, par_2, ... );

Q10. What Is Difference Between Freeze Deposit And Force?

Ans: $deposit(variable, cost);

This machine venture units a Verilog sign in or net to the specified fee. Variable is the check in or internet to be changed; fee is the brand new price for the register or net. The cost stays till there's a subsequent driving force transaction or some other $deposit venture for the equal check in or net. This gadget undertaking operates identically to the ModelSim pressure -deposit command.

The force command has -freeze, -pressure, and -deposit alternatives. When none of those is designated, then -freeze is thought for unresolved signals and -power is thought for resolved indicators. This is designed to offer compatibility with force documents. But in case you decide on -freeze as the default for each resolved and unresolved alerts.

Q11. What Is Meant By Inferring Latches,how To Avoid It?

Ans: Consider the following :

always @(s1 or s0 or i0 or i1 or i2 or i3)

case (s1, s0)

2'd0 : out = i0;

2'd1 : out = i1;

2'd2 : out = i2;

endcase

in a case statement if all of the feasible combinations aren't as compared and default is also not special like in example above a latch could be inferred ,a latch is inferred due to the fact to reproduce the previous cost when unknown branch is specified.

For example in above case if s1,s0=3 , the previous saved price is reproduced for this storing a latch is inferred.

The identical can be determined in IF statement in case an ELSE IF is not detailed.

To keep away from inferring latches make sure that every one the cases are stated if now not default circumstance is provided.

Q12. Tell Me How Blocking And Non Blocking Statements Get Executed?

Ans: Execution of blockading assignments can be regarded as a one-step process:

1. Evaluate the RHS (right-hand facet equation) and replace the LHS (left-hand side expression) of the blocking off undertaking with out interruption from every other Verilog declaration. A blocking off assignment "blocks" trailing assignments inside the equal usually block from happening till after the modern task has been finished

Execution of nonblocking assignments may be viewed as a -step method:

Evaluate the RHS of nonblocking statements at the beginning of the time step.

Update the LHS of nonblocking statements on the quit of the time step.

Q13. Tell Me Structure Of Verilog Code You Follow?

Ans: A desirable template on your Verilog document is shown below.

// timescale directive tells the simulator the base units and precision of the simulation

`timescale 1 ns / 10 playstation 

module name (enter and outputs);

// parameter declarations

parameter parameter_name = parameter price;

// Input output declarations

enter in1;

input in2; // single bit inputs

output [msb:lsb] out; // a bus output

// internal sign check in kind assertion - register sorts (handiest assigned inside continually statements). Reg sign up

variable 1;

reg [msb:lsb] check in variable 2;

// inner signal. Net kind assertion - (best assigned outside always statements) wire net variable 1;

// hierarchy - instantiating some other module

reference name example name (

.Pin1 (net1),

.Pin2 (net2),

.

.Pinn (netn)

);

// synchronous procedures

constantly @ (posedge clock)

begin

.

End

// combinatinal approaches

continually @ (signal1 or signal2 or signal3)

start

.

Quit

assign internet variable = combinational common sense;

endmodule

Q14. Difference Between Verilog And Vhdl?

Ans: Compilation

VHDL. Multiple design-devices (entity/architecture pairs), that live within the identical machine report, can be one by one compiled in that case preferred. However, it is right design exercise to maintain each layout unit in it is own machine report wherein case separate compilation should not be an problem.

Verilog. The Verilog language is still rooted in it is local interpretative mode. Compilation is a means of speeding up simulation, however has now not modified the authentic nature of the language. As a result care have to be curious about both the compilation order of code written in a single record and the compilation order of multiple files. Simulation consequences can exchange by means of surely changing the order of compilation.

Data kinds 

VHDL. A multitude of language or user described facts sorts may be used. This may additionally mean committed conversion features are needed to convert items from one kind to every other. The desire of which records types to apply must be taken into consideration wisely, mainly enumerated (summary) information types. This will make fashions less difficult to put in writing, clearer to read and avoid pointless conversion functions that could litter the code. VHDL may be desired because it lets in a multitude of language or user described records kinds for use.

Verilog. Compared to VHDL, Verilog records kinds a re quite simple, clean to apply and very tons geared closer to modeling hardware shape in preference to summary hardware modeling. Unlike VHDL, all facts kinds used in a Verilog version are defined by means of the Verilog language and not by the user. There are internet information types, as an instance wire, and a register records kind known as reg. A version with a signal whose kind is one of the internet records sorts has a corresponding electric wire inside the implied modeled circuit. Objects, this is alerts, of type reg maintain their price over simulation delta cycles and need to now not be burdened with the modeling of a hardware sign up. Verilog may be preferred because of it is simplicity.

Design reusability 

VHDL. Procedures and functions can be positioned in a package in order that they're avail able to any design-unit that wishes to apply them.

Verilog. There is no concept of packages in Verilog. Functions and processes used inside a version need to be described inside the module. To make functions and tactics normally available from extraordinary module statements the functions and processes need to be located in a separate system file and covered using the `consist of compiler directive.

Q15. Can You List Out Some Of Enhancements In Verilog 2001?

Ans: In in advance version of Verilog ,we use 'or' to specify more than one detail in sensitivity listing . In Verilog 2001, we can use comma as proven in the example below.

// Verilog 2k instance for utilization of comma

constantly @ (i1,i2,i3,i4)

Verilog 2001 lets in us to apply celebrity in sensitive list in place of listing all of the variables in RHS of mixture logics . This removes typo errors and hence avoids simulation and synthesis mismatches,  Verilog 2001 permits port path and information kind inside the port listing of modules as shown in the instance beneath

module reminiscence (

input r,

enter wr,

enter [7:0] data_in,

input [3:0] addr,

output [7:0] data_out

);

Q16. How To Write Fsm Is Verilog?

Ans: there r mainly four ways 2 write fsm code

the use of 1 method in which all input decoder, present state, and output decoder r integrate in one procedure.

The usage of 2 system in which all comb ckt and sequential ckt separated in unique procedure

using 2 procedure where input decoder and persent state r integrate and output decoder seperated in different system

the usage of 3 technique wherein all three, input decoder, present country and output decoder r separated in three process.

HubSpot Video
 

Q17. Write A Verilog Code For Synchronous And Asynchronous Reset?

Ans: Synchronous reset, synchronous way clock dependent so reset ought to no longer be present in sensitivity disk

eg: continually @ (posedge clk )

begin if (reset)

. . . Stop

Asynchronous method clock unbiased so reset ought to be found in sensitivity list.

Eg: Always @(posedge clock or posedge reset)

start

if (reset)

. . . End

Q18. There Is A Triangle And On It There Are three Ants One On Each Corner And Are Free To Move Along Sides Of Triangle What Is Probability That They Will Collide?

Ans: Ants can circulate simplest along edges of triangle in either of direction, permit’s say one is represented by way of 1 and some other through 0, seeing that there are 3 aspects 8 combos are viable, whilst all ants are stepping into identical direction they gained’t collide this is 111 or 000 so chance of now not collision is two/8=1/four or collision probability is 6/eight=three/four

Q19. What Does `timescale 1 Ns/ 1 Ps Signify In A Verilog Code?

Ans: 'timescale directive is a compiler directive.It is used to degree simulation time or put off time. Usage :`timescale / reference_time_unit : Specifies the unit of measurement for times and delays. Time_precision: specifies the precision to which the delays are rounded off.

Q20. What Is The Difference Between === And == ?

Ans: output of "==" can be 1, zero or X.

Output of "===" can most effective be 0 or 1.

When you are comparing 2 nos the usage of "==" and if one/each the numbers have one or extra bits as "x" then the output would be "X" . But if use "===" outpout could be zero or 1.

E.G A = 3'b1x0

B = three'b10x

A == B will supply X as output.

A === B will provide 0 as output.

"==" is used for evaluation of simplest 1's and zero's .It cannot examine Xs. If any little bit of the enter is X output can be X

"===" is used for contrast of X additionally.

Q21. Will Case Infer Priority Register If Yes How Give An Example?

Ans: sure case can infer precedence sign in relying on coding style

reg r;

// Priority encoded mux,

usually @ (a or b or c or select2)

start

r = c;

case (select2)

2'b00: r = a;

2'b01: r = b;

endcase

give up

Q22. Given The Following Verilog Code, What Value Of "a" Is Displayed?

Ans: constantly @(clk) begin

a = zero;

a <= 1;

$show(a);

give up

This is a problematic one! Verilog scheduling semantics essentially mean a four-degree deep queue for the current simulation time:

Active Events (blocking statements)

Inactive Events (#0 delays, etc)

Non-Blocking Assign Updates (non-blocking off statements)

Monitor Events ($show, $screen, and many others).

Since the "a = 0" is an lively occasion, it is scheduled into the first "queue".

The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.

Finally, the display statement is placed into the 4th queue. Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1.

Q23. Why Is It That "if (2'b01 & 2'b10)..." Doesn't Run The True Case?

Ans: This is a popular coding error. You used the bit wise AND operator (&) where you meant to use the logical AND operator (&&).

Q24. What Are Different Types Of Verilog Simulators ?

Ans: There are mainly two types of simulators available.

Event Driven

Cycle Based

Q25. What Is The Difference Between The Following Two Lines Of Verilog Code?

Ans: #5 a = b;

a = #5 b;

#5 a = b;

Wait five time units before doing the action for "a = b;".

A = #5 b; The value of b is calculated and stored in an internal temp register,After five time units, assign this stored value to a.

Q26. How To Generate Sine Wav Using Verilog Coding Style?

Ans: The easiest and efficient way to generate sine wave is using CORDIC Algorithm.

Q27. What Is The Difference Between Wire And Reg?

Ans: (wire,tri)Physical connection between structural elements. Value assigned by a continuous assignment or a gate output. Register type: (reg, integer, time, real, real time) represents abstract data storage element. Assigned values only within an always statement or an initial statement. The main difference between wire and reg is wire cannot hold (store) the value when there no connection between a and b like a->b, if there's no connection in a and b, cord loose cost. But reg can keep the cost even though there in no connection. Default values:cord is Z,reg is x.