Interview Questions.

Q1. Can A Master Change The Address/manage Signals During A Waited Trfer?

Yes. If the deal with/manipulate indicators are indicating an IDLE trfer then the grasp can trade to a real trfer (NONSEQ) while HREADY is low.

However, if a grasp is indicating a real trfer (NONSEQ or SEQ) then it can not cancel this all through a waited trfer except it gets a SPLIT, RETRY or ERROR response.

Q2. What Is The State Of The Ahb Signals During Reset?

The specification states that during reset the bus signals should be at valid stages. This certainly me that the indicators must be logic '0' or '1', but now not Hi-Z. The actual logic tiers pushed are left up to the fashion designer. HTRANS is the most effective signal detailed for the duration of reset, with a mandatory price of IDLE.

It is important that ALREADY is high at some stage in reset. If all slaves within the machine drive HARDY excessive for the duration of reset then this will make sure that that is the case. However, if slaves are used which do no longer pressure HREADY high in the course of reset it need to be ensured that a slave which does force HREADY excessive is chosen at reset.

Q3. Can A Slave Assert Hsplitx In The Same Cycle That It Gives A Split Response?

No. The specification requires that HSPLITx can simplest be asserted after the slave has given a SPLIT response.

Q4. Do All Slaves Have To Support The Split And Retry Responses?

No. A slave is handiest required to aid the reaction sorts that it desires to apply. For example, a easy on-chip reminiscence block which could reply to all trfers in just a few wait states does now not want to apply either the SPLIT or RETRY responses.

Q5. Can A Master Deassert Hlock During A Burst?

The AHB specification requires that each one address section timed manage signals (other than HADDR and HTRANS) continue to be consistent during a burst.

Although HLOCK isn't an cope with segment timed signal, it does at once control the HMASTLOCK signal which is address segment timed.

Therefore HLOCK ought to remain excessive during a burst, and may simplest be deasserted such that the following HMASTLOCK sign modifications after the very last cope with segment of the burst.

Q6. Is It Legal For A Master To Change Haddr When A Trfer Is Extended?

If a master is indicating that it wants to do a NONSEQ, SEQ or BUSY trfer then it can not change the cope with throughout an extended trfer(while HREADY is low) except it gets an ERROR, RETRY or SPLIT response.

If the grasp is indicating that it wants to do an IDLE trfer then it is able to exchange the cope with.

Q7. When Can The Hgrant Signal Change?

The GRANT sign can alternate in any cycle and the subsequent instances are feasible:

It is possible that the HGRANT signal may be asserted and then eliminated earlier than the modern trfer completes. This is appropriate due to the fact the HGRANT signal is most effective sampled via masters whilst HREADY is high.

A master may be granted the bus with out inquiring for it.

The above point additionally me that it is possible to be granted the bus within the equal cycle that it is requested. This can occur if the grasp is coincidentally granted the bus inside the same cycle that it requests it.

Q8. The Specification Recommends That Only 16 Wait States Are Used. What Should You Do If More Than 16 Cycles Are Needed?

For a few slaves it's far desirable to insert greater than 16 wait states. For instance, a serial boot ROM that is handiest ever accessed at preliminary power up ought to insert a bigger range of wait states and it'd now not affect the calculation of the system overall performance and latency as soon as gadget strength up has been finished.

For other slaves a number of options exist. A SPLIT or RETRY response can be used to signify that the slave isn't always but able to perform the requested statistics trfer, or the slave might be accessed both in response to interrupts or after polling a standing sign in, in both case indicating that the slave is now capable of reply in a suitable quantity of cycles.

Q9. Is Hready An Input Or An Output From Slaves?

An AHB slave need to have the HREADY signal as each an enter and an output.

HREADY is needed as an output from a slave in order that the slave can amplify the statistics phase of a trfer.

HREADY is likewise required as an enter so that the slave can decide whilst the previously selected slave has completed its final trfer and the primary records section trfer for this slave is ready to start.

Each AHB Slave should have an HREADY output signal (conventionally named HREADYOUT) that is related to the Slave-to-Master Multiplexer. The output of this multiplexer is the global HREADY sign that's routed to all masters on the AHB and is also fed lower back to all slaves because the HREADY enter.

Q10. Will A Master Always Lose The Bus After A Split Response?

Yes. A slave have to now not assert the relevant little bit of the SPLIT bus inside the identical cycle that it offers the SPLIT response and consequently the grasp will always lose the bus.

Q11. Is A Default Slave Really Necessary?

If the complete 4 gigabyte address space is defined then a default slave isn't required. If, but, there are undefined areas within the memory map then it's miles critical to make sure that a spurious get right of entry to to a non-existent address region will now not lock up the gadget. The functionality of the default slave is extremely easy and it'll regularly make feel to implement this within the decoder.

Q12. Can An Ahb Master Be Connected Directly To An Ahb Slave?

Any slave which does not use SPLIT responses may be related immediately to an AHB grasp. If the slave does use SPLIT responses then a simplified version of the arbiter is also required.

If an AHB grasp is connected without delay to an AHB slave it's far crucial to make certain that the slave drives HREADY high in the course of reset and that the pick out sign HSEL for the slave is tied completely excessive.

Q13. What Value Should Be Used For Htr When An Ahb Master Gets A Retry Response From A Slave In The Middle Of Burst?

Whenever a trfer is restarted it need to use HTRANS set to NONSEQ and it could also be vital to adjust the HBURST statistics (normally just to suggest INCR).

Q14. How Many Masters Can There Be In An Ahb System?

The AHB specification caters for up to sixteen masters. However, making an allowance for a dummy bus grasp me the most range of real bus masters is in reality @By convention bus master quantity 0 is allocated to the dummy bus grasp.

Q15. When Will The Arbiter Grant Another Master After A Locked Trfer?

The arbiter will constantly provide the master a further trfer at the cease of a locked series, so the grasp is guaranteed to carry out one trfer with the HMASTLOCK signal low at the quit of the locked series. This coincides with the facts phase of the ultimate trfer inside the locked collection.

During this time the arbiter can change the HGRANT alerts to a brand new bus grasp, but if the statistics section of the ultimate locked trfer receives either a SPLIT or RETRY response then the arbiter will drive the HGRANT signals to make sure that both the master acting the locked series remains granted on the bus for a RETRY reaction, or the Dummy master is granted the bus for the SPLIT response.

Q16. What Is The Difference Between Split And Retry Responses?

Both the Split and Retry responses are used by slaves which require a large number of cycles to complete a trfer. These responses allow a information phase trfer to appear finished to keep away from stalling the bus, but on the equal time suggest that the trfer need to be re-tried whilst the grasp is subsequent granted the bus.

The distinction between them is that a SPLIT response tells the Arbiter to give precedence to all other masters till the SPLIT trfer may be finished (effectively ignoring all further requests from this master until the SPLIT slave suggests it could complete the SPLIT trfer), whereas the RETRY reaction most effective tells the Arbiter to offer precedence to better priority masters.

A SPLIT reaction is more complex to implement than a RETRY, but has the advantage that it permits the maximum efficiency to be product of the bus bandwidth.

The master behaviour is same to each SPLIT and RETRY responses, the grasp has to cancel the next get entry to and re-try the cutting-edge failed access.

Q17. If A Master Is Currently Granted The Bus By Default, How Many Cycles Before Starting An Non-idle Trfer Does It Have To Assert Hbusreq?

None. It can begin a non IDLE trfer at once.

Q18. Can A Master Perform Trfers Other Than Idle When The Bus Was Granted To It, But Not Requested By The Master?

Yes. A grasp can carry out trfers apart from IDLE while it had not requested the bus. Please word that during this case it's far still endorsed that the master asserts its request signal so that the arbiter does no longer trade ownership of the bus to a decrease priority grasp whilst the trfers are in progress.

Q19. What Is The Difference Between A Dummy Bus Master And A Default Bus Master?

The term default bus master is used to explain the master this is granted when none of the masters within the gadget are asking for get entry to to the bus. Usually the bus grasp that is maximum probably to request the bus is made the default grasp.

The dummy bus master is a master which best plays IDLE trfers. It is required in a machine so the arbiter can furnish a master that's assured no longer to perform any actual trfers. The  cases whilst the arbiter might want to do this are while a SPLIT reaction is given to a locked trfer and whilst a SPLIT response is given and all different masters have already been SPLIT.

Q20. When Should A Master Assert And Deassert The Block Signal For A Locked Trfer?

The GLOCK sign should be asserted at least one cycle before the start of the address section of a locked trfer. This is required so that the arbiter can sample the HLOCK signal as excessive on the begin of the address phase.

The grasp must deassert the HLOCK sign whilst the cope with section of the ultimate trfer in the locked collection has started out.

Q21. Can An Arbiter Be Designed To Always Allow Bursts To Complete?

A SPLIT, RETRY or ERROR reaction from a slave can constantly cause a burst to be early terminated. This is outwith the manipulate of the Arbiter and so ought to be supported.

Undefined duration INCR bursts can not have their cease point predicted, so there's no green manner that an Arbiter design can permit the burst to complete before granting some other grasp. INCR bursts have to be arbitrated ona cycle with the aid of cycle basis.

Defined duration INCRx and WRAPx bursts will have their beats counted, and so allowed to finish by way of the Arbiter. However due to the AHB arbitration synchronous timing, there may be no way to keep away from probably terminating a burst without delay after the primary trfer of the burst has been indicated.

The Arbiter handiest knows that a described duration burst is in progress with the aid of sampling the HBURST bus. However the first point at which HBURST can be sampled is after the primary clock cycle of the first burst beat, by means of which time the Arbiter might also already have determined to furnish another master and could have modified the HGRANT outputs therefore. Only a combinatorial route from HBURST to HGRANT might permit the burst to be detected in time to avoid early termination on this situation, but combinatorial paths inside the AHB bus aren't allowed.

Q22. Can A Split Or Retry Response Be Given At Any Point During A Burst?

Yes. A SPLIT, RETRY or ERROR reaction can be given via a slave to any trfer at some point of a burst. The slave is not constrained to most effective giving these responses to the primary trfer.

Q23. Does The Address Have To Be Aligned, Even For Idle Trfers?

Yes. The cope with need to be aligned in keeping with the trfer size (HSIZE) even for IDLE trfers. This will save you spurious warnings from bus video display units used at some point of simulation.

Q24. What Is The Recommended Default Value For Hprot?

Many bus masters will now not be able to generate accurate protection records and for those bus masters it's miles endorsed that the HPROT encoding shows, Non-cacheable, Non-bufferable, Privileged, Data Accesses which corresponds to HPROT[3:0] = 4'b0011.

Q25. When Can Early Burst Termination Occur?

Bursts may be early terminated both as a result of the Arbiter removing the HGRANT to a grasp part way through a burst, or after a slave returns a non-OKAY response to any beat of a burst. Note but that a grasp can't determine to terminate a defined length burst until triggered to accomplish that by the Arbiter or Slave responses.

All AHB Masters, Slaves and Arbiters have to be designed to guide Early Burst Termination.

Q26. Can A Busy Trfer Occur At The End Of A Burst?

A BUSY trfer can simplest occur on the stop of an undefined length burst (INCR). A BUSY trfer cannot occur on the cease of a hard and fast period burst (SINGLE, INCR4, WRAP4, INCR8, WRAP8, INCR16, WRAP16).

Q27. Is It Specified That Hprot, Hsize And Hwrite Remain Constant Throughout A Burst?

Yes, the manipulate indicators need to remain steady for the duration of the length of a burst.

Q28. How Should Ahb To Apb Bridges Handle Accesses That Are Not 32-bits?

The bridge must simply bypass the complete 32-bit records bus via the bridge. Please notice that when trfers less than 32-bits are completed to an APB slave it's miles essential to make sure that the peripheral is placed on an appropriate bits of the APB facts bus.

Q29. What System Support Is Required If A Slave Can Be Powered Down Or Have Its Clock Stopped?

If a slave access is attempted even as that slave is in a strength down country or has had its clock stopped, you need to ensure that an access will motive the electricity/clock to be restored, otherwise configure the AHB decoder up to redirect this type of accesses to the dummy slave in order that the system does now not dangle forever when an get right of entry to to the tool is made whilst it's far disabled.

Redirecting the get entry to on this manner will make sure that random "IDLE" addresses are treated with the HREADY high and HRESP=OKAY default reaction, but real accesses (NONSEQ or SEQ) could be detected with an ERROR response.

Q30. Can Htr Change Whilst Hready Is Low?

In widespread, an AHB master have to now not alternate control alerts whilst HREADY is low.

However it is allowable to alternate HTRANS inside the following situations:

HTRANS = IDLE

The AHB grasp is acting inner operations and has no longer but committed to a bus trfer. However during the AHB wait states (HREADY low) the master might also determine that a bus trfer is needed and alternate

HTRANS on the subsequent cycle to NONSEQ.

HTRANS = BUSY

HTRANS is being used to present the grasp time to complete internal operations, which can be totally independent of HREADY (i.E. Wait states on the AHB). Therefore HTRANS can exchange on the next cycle to any legal cost, i.E. SEQ if the burst is to keep, IDLE if the burst has completed, NONSEQ if a separate burst is to begin.

HRESP = SPLIT/RETRY

As stated in the AHB specification, a grasp ought to assert IDLE on HTRANS at some point of the second cycle of the 2-cycle SPLIT or RETRY slave reaction so HTRANS will trade price from the primary cycle to the second cycle of the reaction.

HRESP = ERROR

The master is authorized to alternate HTRANS in response to an ERROR response in the same way as in reaction to a SPLIT/RETRY reaction and cancel any in addition beats in the current burst (even though HBURST is indicating a defined-length burst). In this case HTRANS modifications to IDLE on the second cycle of the reaction. Alternatively, the master is allowed to maintain with the present day trfers

Q31. What Are The Different Bursts Used For?

Typically a master could use wrapping bursts for cache line fills where the grasp desires to get entry to the data it calls for first and then it completes the burst to fetch the last records it requires for the cache line fill.

Incrementing bursts are used by masters, together with DMA controllers, which are filling a buffer in memory which won't be aligned to a specific deal with boundary.

Q32. Can A Slave Use Both Split And Retry Responses?

Normally a slave will not use both the SPLIT and RETRY responses. The SPLIT response should be utilized by any slave that may be accessed by means of many distinctive masters on the same time. The RETRY response is supposed to be used by peripherals which are best accessed by using one bus master.

Q33. Is A Dummy Master Really Necessary?

A dummy master is important in any gadget which has a slave that could deliver SPLIT trfer responses. The dummy master is needed in order that something can be granted the bus if all the different masters have acquired a SPLIT response.

No logic is required for the dummy grasp and it is able to be applied through certainly tying off the inputs to the grasp deal with/control multiplexer for the dummy grasp role. The necessities for a dummy master are that HTRANS is pushed to IDLE, GLOCK is driven low, and all other grasp outputs are pushed to prison values.

Q34. Do All Slaves Have To Support The Busy Trfer Type?

Yes. All slaves have to support the BUSY trfer kind to make sure they're well suited with any bus grasp.

Q35. What Is The Relationship Between The Hlock Signal And The Hmastlock Signal?

At the begin of the address segment of every trfer the arbiter will sample the HLOCK signal of the grasp that is about to start riding the address bus and if HLOCK is declared at this factor then HMASTLOCK may be asserted by the arbiter for the duration of the deal with segment of the trfer.

Q36. What Address Should Be On The Bus During The Idle Cycle After A Split Or Retry?

It does no longer remember what cope with is pushed onto the bus during this cycle.

The slave decided on by using the driven deal with need to now not take any motion and should respond with a 0 wait country OKAY reaction.

In many cases it will be less complicated for the master to depart the address unaltered at some point of this cycle, so that it remains on the cope with of the next trfer that the master wishes to carry out and most effective inside the following cycle does the master go back the cope with to that of the trfer that need to be repeated because of the SPLIT or RETRY reaction.

In a few designs it could be feasible for the grasp to go back the cope with to that required to copy the previous trfer in the course of the IDLE cycle and this behaviour is also perfectly suited.

Q37. Do All Masters Have To Support Split And Retry?

Yes. All masters must assist SPLIT and RETRY responses to make sure they may be well matched with any bus slave. A grasp will handle each SPLIT and RETRY responses in an equal way.

Q38. When Should A Master Deassert Its Hbusreq Signal?

For an undefined period burst (INCR) a master need to keep its HBUSREQ signal asserted till it has started out the cope with phase of the ultimate trfer within the burst. This will mean that if the penultimate trfer in the burst is zero wait country then the grasp may be granted the bus for an additional trfer on the stop of an undefined duration burst.

For a described duration burst the master can deassert the HBUSREQ signal as soon as the grasp has been granted the bus for the first trfer. This may be performed because the arbiter is capable of count the trfers within the burst and maintain the grasp granted until the burst completes.

However it is not a mandatory requirement for an Arbiter to allow a burst to finish, so the master will need to re-assert HBUSREQ if the Arbiter gets rid of HGRANT earlier than the burst has been completed.

Q39. What Is A Default Slave?

If the reminiscence map of a gadget does now not define the overall 4 gigabyte cope with space then a default slave is needed, which is chosen while an get entry to is tried to the empty areas of the reminiscence map. The default slave must use an OKAY response for IDLE/BUSY trfers and an ERROR reaction collection for NONSEQ/SEQ trfers.

Q40. What Default State Should Be Used For The Hready And Hresp Outputs From A Slave?

It is recommended that the default fee for HREADY is high and the default fee for HRESP is OKAY. This aggregate ensures that the slave will respond correctly to IDLE trfers to the slave, even supposing the slave is in a few shape of strength saving mode.

Q41. When A Master Rebuilds A Burst Which Has Been Terminated Early Are There Any Limitations On How It Rebuilds The Burst?

The best hindrance is that the grasp uses criminal burst combinations to rebuild the burst. For instance, if a master was appearing an 8 beat burst, but had handiest completed three trfers earlier than losing manage of the bus, then the ultimate 5 trfers might be achieved both through the usage of a 1 beat SINGLE burst followed through a four beat INCR burst, or it is able to be executed using a five beat undefined period INCR burst.

For simplicity it is advocated that masters use INCR bursts to rebuild the ultimate trfers.

Q42. Why Is A Burst Not Allowed To Cross A 1 Kilobyte Boundary?

If an AHB slave samples HSELx at the begin of a burst traction, it knows it'll be decided on during the burst. Also, a slave which isn't always selected on the start of a burst will know that it'll not end up selected till a new burst is started out.

1 kilobyte is the smallest area an AHB slave may additionally occupy inside the memory map.

Therefore, if a burst did move a 1 kilobyte boundary, the get right of entry to could start getting access to one slave at the start of the burst after which switch to another at the boundary, which need to no longer manifest for the above reason.

The 1 kilobyte boundary has been selected as it is huge sufficient to allow reasonable period bursts, but small enough that peripherals may be aligned to the 1 kilobyte boundary without the use of up an excessive amount of of the to be had reminiscence map.

Q43. Why Is Haddr Sometimes Shown As An Input To The Arbiter?

The cope with bus, HADDR, isn't always required as an enter to the arbiter however in a few machine designs it can be useful to apply the address bus to decide an amazing point to exchange over among bus masters. For example, the arbiter may be designed to trade bus ownership whilst a burst of trfers reaches a quad word boundary.