Interview Questions.

Q1. What Is Difference Between Ram And Fifo?

FIFO does not have cope with lines

Ram is used for garage reason wherein as FIFO is used for synchronization purpose i.E. Whilst  peripherals are operating in one of a kind clock domain names then we can move for FIFO.

Q2. What Is Significance Of Ras And Cas In Sdram?

SDRAM receives its cope with command in two address words. It makes use of a multiplex scheme to keep input pins. The first deal with phrase is latched into the DRAM chip with the row address strobe (RAS).

Following the RAS command is the column address strobe (CAS) for latching the second one deal with phrase. Shortly after the RAS and CAS strobes, the saved statistics is valid for studying.

Q3. Convert D-ff Into Divide By

T_setup= 6nsT_hold = 2nS T_propagation = 10nS

Circuit: Connect Qbar to D and practice the clk at clk of DFF and take the O/P at Q. It gives freq/@Max. Freq of operation: 1/ (propagation postpone+setup time) = 1/16ns = 62.Five MHz

Q4. What Will Happen If Contents Of Register Are Shifter Left, Right?

It is widely known that during left shift all bits could be shifted left and LSB may be appended with zero and in proper shift all bits may be shifted right and MSB will be appended with zero this is a trustworthy wer What is expected is in a left shift cost gets Multiplied by means of 2

e.G.: keep in mind 0000_1110=14 a left shift will make it 0001_110=28, it the equal style right shift will Divide the cost by 2.

Q5. Give Two Ways Of Converting A Two Input Nand Gate To An Inverter?

A) Short the two inputs of the nand gate and follow the single input to it.

B) Connect the output to one of the input and the other to the enter sign.

Q6. Difference Between Mealy And Moore State Machine?

A) Mealy and Moore fashions are the basic fashions of kingdom machines. A state gadget which uses best Entry Actions, so that its output relies upon on the country, is called a Moore version. A state machine which makes use of handiest Input Actions, so that the output depends at the country and additionally on inputs, is known as a Mealy version. The models decided on will impact a design but there are no trendy indications as to which model is better. Choice of a version depends on the software, execution me (for example, hardware structures are generally high-quality found out as Moore fashions) and private options of a clothier or programmer

B) Mealy system has outputs that depend on the country and input (consequently, the FSM has the output written on edges) Moore machine has outputs that rely upon state most effective (as a consequence, the FSM has the output written within the kingdom itself.

Advantage and Disadvantage

•In Mealy because the output variable is a function both enter and state, modifications of nation of the kingdom variables may be not on time with admire to modifications of sign stage in the enter variables, there are possibilities of system defects acting inside the output variables.

•Moore overcomes glitches as output dependent on most effective states and now not the enter signal degree.

•All of the principles may be implemented to Moore-version nation machines due to the fact any Moore kingdom system may be applied as a Mealy state system, although the communicate isn't always proper.

•Moore gadget: the outputs are residences of states themselves... Which me that you get the output after the gadget reaches a selected nation, or to get some output your device needs to be taken to a state which offers you the output. The outputs are held until you visit a few other kingdom Mealy device:

•Mealy machines come up with outputs immediately, that is without delay upon receiving input, but the output is not held after that clock cycle.

Q7. What Is A Multiplexer?

Is a combinational circuit that selects binary information from one in every of many enter lines and directs it to a unmarried output line.

(2n =>n). Where n is selection line.

Q8. Differences Between D-latch And D Flip-flop?

D-latch is stage sensitive wherein as turn-flop is facet touchy. Flip-flops are made from latches.

Q9. Tell Some Of Applications Of Buffer?

A) They are used to introduce small delays.

B) They are used to get rid of cross communicate brought on because of inter electrode capacitance because of close routing.

C) They are used to help excessive fan-out, e.G.: bufg

Q10. How Can You Convert The Jk Flip-flop To A D Flip-flop?

By connecting the J enter to the K via the inverter.

Q11. How Can You Convert An Sr Flip-flop To A Jk Flip-flop?

By giving the comments we can convert, i.E. !Q=>S and Q=>R.Hence the S and R inputs will act as J and K respectively.

Q12. Implement The Following Circuits:

(a) 3 enter NAND gate the usage of min no of two input NAND Gates

(b) 3 enter NOR gate the use of min no of two enter NOR Gates

(c) three enter XNOR gate the use of min no of two input XNOR Gates

Assuming three inputs A,B,C?

3 enter NAND Connect:

a) A and B to the first NAND gate

b) Output of first Nand gate is given to the two inputs of the second NAND gate (this essentially realizes the inverter capability)four

c) Output of 2d NAND gate is given to the enter of the third NAND gate, whose other enter is C ((A NAND B) NAND (A NAND B)) NAND C Thus, may be implemented the use of 'three' 2-enter NAND gates. I bet this is the minimal wide variety of gates that want to be used.

Q13. What Is Difference Between Setup And Hold Time. The Interviewer Was Looking For One Specific Reason, And Its Really A Good Answer Too..The Hint Is Hold Time Doesn't Depend On Clock, Why Is It So...?

Setup violations are associated with  edges of clock, i suggest you can vary the clock frequency to accurate setup violation. But for keep time, you're most effective concerned with one area and do now not essentially depend upon clock frequency.

Q14. An Assembly Line Has 3 Fail Safe Sensors And One Emergency Shutdown Switch. The Line Should Keep Moving Unless Any Of The Following Conditions Arise:

(i) If the emergency transfer is pressed

(ii) If the senor1 and sensor2 are activated at the same time.

(iii) If sensor 2 and sensor3 are activated on the same time.

(iv) If all the sensors are activated at the equal time

suppose a combinational circuit for above case is to be carried out only with NAND Gates. How many minimal wide variety of two enter NAND gates are required?

No of two-enter NAND Gates required = 6 you could strive the entire implementation.

Q15. You Have Two Counters Counting Upto sixteen, Built From Negedge Dff , First Circuit Is Synchronous And Second Is "ripple" (cascading), Which Circuit Has A Less Propagation Delay? Why?

The synchronous counter could have lesser postpone as the input to every flop is with ease to be had before the clock facet. Whereas the cascade counter will take long term because the output of one flop is used as clock to the other. So the delay will be propagating. For E.G.: sixteen nation counter = four bit counter = four Flip flops Let 10ns be the postpone of every flop The worst case postpone of ripple counter = 10 * four = 40ns The delay of synchronous counter = 10ns simplest.(Delay of 1 flop)

Q16. What Are Set Up Time & Hold Time Constraints? What Do They Signify? Which One Is Critical For Estimating Maximum Clock Frequency Of A Circuit?

Set up time is the amount of time the statistics should be solid earlier than the software of the clock sign, wherein as the preserve time is the amount of time the records should be strong after the application of the clock. Setup time indicates most delay constraints; maintain time is for minimum postpone constraints. Setup time is critical for setting up the most clock frequency.

Q17. The Circle Can Rotate Clockwise And Back. Use Minimum Hardware To Build A Circuit To Indicate The Direction Of Rotating?

2 sensors are required to find out the course of rotating. They are located like at the drawing. One of the m is connected to the statistics enter of D flip-flop, and a second one - to the clock enter. If the circle rotates the way clock sensor sees the light first while D input (2d sensor) is 0 - the output of the turn-flop equals zero, and if D enter sensor "fires" first - the output of the turn-flop becomes high.

Q18. Why Is Most Interrupts Active Low?

This wers why maximum signals are active low in case you recall the tristor level of a module, active low me the capacitor inside the output terminal gets charged or discharged based totally on low to high and excessive to low trition respectively. When it goes from excessive to low it depends on the pull down resistor that attracts it down and it's miles exceedingly clean for the output capacitance to discharge rather than charging. Hence people choose the usage of energetic low signals.

Q19. How Will You Implement A Full Subtractor From A Full Adder?

All the bits of subtrahend ought to be related to the xor gate. Other enter to the xor being one. The enter convey bit to the entire adder have to be made @Then the entire adder works like a full subtract.

Q20. Design All The Gates (no longer, And, Or, Nand, Nor, Xor, Xnor) Using 2:1 Multiplexer?

Using 2:1 Mux, (2 inputs, 1 output and a pick out line)

a) NOT :Give the input on the pick line and join I0 to 1 & I1 to @So if A is 1, we will get I1 this is zero on the O/P.

B) AND: Give enter A at the pick line and 0 to I0 and B to I@O/p is A & B

c) OR: Give enter A on the select line and 1 to I1 and B to I@O/p can be A collectively

e) NOR: OR + NOT implementations together

f) XOR: A on the pick line B at I0 and ~B at I@~B may be obtained from (a)

g) XNOR: A at the pick out line B at I1 and ~B at I0

Q21. How To Achieve a hundred and eighty Degree Exact Phase Shift?

Never inform using inverter

a) DCM an built in aid in most of FPGA may be configured to get one hundred eighty diploma segment shift.

B) BUFGDS this is differential signaling buffers which might be also inbuilt resource of most of FPGA may be used.

Q22. In A three-bit Johnson's Counter What Are The Unused States?

2(strength n)-2n is the only used to locate the unused states in Johnson counter.

So for a three-bit counter it is 8-6=2.Unused states=@the two unused states are 010 and one hundred and one.

Q23. Difference Between Synchronous And Asynchronous Reset?

Synchronous reset logic will synthesize to smaller flip-flops, in particular if the reset is gated with the common sense generating the dinput. But in this kind of case, the combinational logic gate count grows, so the overall gate depend financial savings won't be that sizeable. The clock works as a clear out for small reset glitches; but, if those system faults occur close to the energetic clock edge, the Flip-flop ought to move metastable. In some designs, the reset have to be generated via a set of internal conditions. A synchronous reset is suggested for those sorts of designs as it will clear out the logic equation system defects among clocks.

Disadvantages of synchronous reset:

Problem with synchronous resets is that the synthesis device can not without problems distinguish the reset sign from every other records signal. Synchronous resets might also want a pulse stretcher to guarantee a reset pulse width huge sufficient to make certain reset is gift in the course of an active fringe of the clock. When you have a gated clock to keep energy, the clock may be disabled coincident with the statement of reset. Only an asynchronous reset will paintings in this situation, as the reset might be eliminated previous to the resumption of the clock. Designs that are pushing the limit for information path timing, cannot manage to pay for to have added gates and further net delays in the information route because of common sense inserted to handle synchronous resets.

Asynchronous reset:

The largest hassle with asynchronous resets is the reset release, also referred to as reset elimination. Using an asynchronous reset, the dressmaker is assured now not to have the reset added to the records direction. Another advantage favoring asynchronous resets is that the circuit can be reset without or with a clock present.

Disadvantages of asynchronous reset: make sure that the discharge of the reset can occur inside one clock period. If the release of the reset befell on or near a clock side such that the turn-flops went metastable.

Q24. How Do You Detect If Two 8-bit Signals Are Same?

XOR each bits of A with B (for e.G. A [0] xor B [0]) and so forth. The o/p of eight xor gates is then given as i/p to an 8-i/p nor gate.

If o/p is 1 then A=B.

Q25. What Is Difference Between Latch And Flip-flop?

The primary distinction among latch and FF is that latches are degree sensitive even as FF is side touchy. They both require the usage of clock signal and are utilized in sequential logic. For a latch, the output tracks the enter while the clock sign is excessive, so as long as the clock is logic 1, the output can alternate if the enter additionally adjustments.

FF alternatively, will store the enter handiest whilst there is a rising/falling fringe of the clock. Latch is touchy to system faults on enable pin, whereas flip-flop is proof against system defects. Latches take fewer gates (additionally less energy) to implement than turn-flops. Latches are quicker than turn-flops

Q26. What Is Race-round Problem? How Can You Rectify It?

The clock pulse that remains in the 1 state whilst each J and K are identical to at least one will purpose the output to supplement once more and repeat complementing until the heart beat goes back to zero, this is known as the race around trouble. To keep away from this undesirable operation, the clock pulse should have a time length this is shorter than the propagation delay time of the F-F, this is restrictive so the opportunity is master-slave or aspect-induced construction.

Q27. Design A Circuit That Calculates The Square Of A Number?

It should now not use any multiplier circuits. It ought to use Multiplexers and different logic?

1^2=0+1=1

2^2=1+3=4

three^2=four+five=nine

4^2=9+7=sixteen

five^2=sixteen+nine=25

See a sample but? To get the subsequent rectangular, all you have to do is add the next extraordinary variety to the previous rectangular that you determined. See how 1,three,5,7 and finally 9 are brought. Wouldn’t this be a possible way to your question because it best will use a counter, multiplexer and multiple adders? It appears it'd take n clock cycles to calculate rectangular of n.

Q28. Difference Between One Hot And Binary Encoding?

Common classifications used to explain the state encoding of an FSM are Binary (or fantastically encoded) and One hot.

A binary-encoded FSM layout most effective requires as many flip-flops as are had to uniquely encode the number of states in the country machine. The actual variety of flip-flops required is equal to the ceiling of the log-base-2 of the number of states in the FSM.A one warm FSM layout calls for a turn-flop for each kingdom inside the layout and most effective one flip-flop (the turn-flop representing the contemporary or "hot" kingdom) is ready at a time in a one hot FSM layout.

For a kingdom gadget with nine- 16 states, a binary FSM handiest calls for four turn-flops while a one hot FSM calls for a flip-flop for every nation inside the layout FPGA carriers frequently suggest the use of a one hot kingdom encoding style due to the fact turn-flops are plentiful in an FPGA and the combinational common sense required to enforce a one hot FSM layout is normally smaller than most binary encoding patterns.

Since FPGA performance is usually associated with the combinational logic size of the FPGA design, one warm FSMs commonly run quicker than a binary encoded FSM with large combinational good judgment blocks

Q29. Given Only Two Xor Gates One Must Function As Buffer And Another As Inverter?

Tie one in all xor gates enter to at least one it will act as inverter.

Tie one among xor gates enter to 0 it will act as buffer.

Q30. 7 Bit Ring Counter's Initial State Is 01000

6 cycles

Q31. Design A Four-input Nand Gate Using Only Two-enter Nand Gates.

Basically, you may tie the inputs of a NAND gate together to get an inverter.

Q32. Consider Two Similar Processors, One With A Clock Skew Of 100ps And Other With A Clock Skew Of 50ps. Which One Is Likely To Have More Power? Why?

Clock skew of 50ps is much more likely to have clock power. This is due to the fact it's far in all likelihood that low-skew processor has higher designed clock tree with greater effective and number of buffers and overheads to make skew higher.

Q33. N Number Of Xnor Gates Is Connected In Series Such That The N Inputs (a0, A1, A2......) Are Given In The Following Way: A0 & A1 To First Xnor Gate And A2 & O/p Of First Xnor To Second Xnor Gate And So

If N=Odd, the circuit acts as even parity detector, i.E. The output will 1 if there are even number of one's within the N input...This can also be called as strange parity generator considering that with this extra 1 as output the whole number of one's could be ODD. If N=Even, simply the alternative, it is going to be Odd parity detector or Even Parity Generator.

Q34. Is It Possible To Reduce Clock Skew To Zero? Explain Your Answer?

Even though there are clock format techniques (H-tree) that may in theory lessen clock skew to 0 through having the same course length from every flip-flop from the pll, method versions in R and C across the chip will motive clock skew in addition to a pure H-Tree scheme isn't realistic (consumes an excessive amount of location).

Q35. Given The Following Fifo And Rules, How Deep Does The Fifo Need To Be To Prevent Underflow Or Overflow?

RULES:

1) frequency(clk_A) = frequency(clk_B) / 4

2) period(en_B) = length(clk_A) * one hundred

three) duty cycle(en_B) = 25%

Assume clk_B = 100MHz (10ns)

From (1), clk_A = 25MHz (40ns)

From (2), length(en_B) = 40ns * four hundred = 4000ns, but we most effective output for 1000ns,due to (3), so 3000ns of the permit we are doing no output paintings. Therefore, FIFO length = 3000ns/40ns = 75 entries