Interview Questions.

Q1. Give Two Ways Of Converting A Two Input Nand Gate To An Inverter?

One manner is shorting the 2 inputs of the NAND gate and passing the enter.

Reality table:

A B output

1 1 0

zero 0 1

The 2nd manner is passing the input to simplest one enter(say A) of the NAND gate.Since the other input(say B) is floating, it is constantly good judgment one.

Reality desk:

A B output

1 1 zero

0 1 1

Q2. Explain What Is Trmission Gate-based totally D-latch?

The Trmission-Gate enter is hooked up to the D_LATCH information enter (D), the manage input to the Trmission-Gate is attached to the D_LATCH allow enter (EN) and the Trmission-Gate output is the D_LATCH output (Q).

Q3. How To Design A Divide-with the aid of-3 Sequential Circuit With 50% Duty Circle?

Take a counter with 3 f/f's that is to mention with 6 states(2*3) now double the i/p clock frequency to the counter the o/p of the 3rd f/f is divide via 6 of the i/p with 50% responsibility cycle so effectively u were given divide by three freq with 50% duty cycle.

Q4. Give The Truth Table For A Half Adder. Give A Gate Level Implementation Of The Same?

TRUTH TABLE FOR HALF ADDER:

A B SUM CARRY

0 zero 0 0

0 1 1 0

1 0 1 zero

1 1 0 1

IMPLEMENTATION:

For SUM, The  inputs A and B are given to XOR gate.

For Carry, The  inputs A and B are given to AND gate.

Q5. How To Detect Sequence Of "1101" Arriving Serially From Signal Line?

Sequence detector : A series detector gives an output of one on detecting the given collection else the output is 0.

Ex : if the given sequence to be detected is 111

and input move is 1 1 0 1 1 1 zero 0 1 zero 1 1 1 1 1

the output need to be zero 0 zero zero 0 1 0 0 0 0 0 0 1 1 1.

Soln:

One of the extraordinary possible methods to hit upon a chain is the usage of a Mealy kind FSM.

Using the subsequent table the State system can be designed.

Q6. Draw A Trmission Gate-based D-latch?

The Trmission-Gate's input is attached to the D_LATCH data input (D), the control input to the Trmission-Gate is connected to the D_LATCH permit enter (EN) and the Trmission-Gate output is the D_LATCH output (Q)

Q7. Which Are The Two Ways Of Converting A Two Input Nand Gate To An Inverter?

Short the two inputs of the nand gate and deliver the identical input to the not unusual wire,the nand gate works as an inverter.

One manner is shorting the 2 inputs of the NAND gate and passing the input.

Fact desk:

A B output

1 1 0 

zero 0 1

The second way is passing the input to simplest one input(say A) of the NAND gate.Since the opposite input(say B) is floating, it's far always common sense one.

Truth table:

A B output

1 1 0

0 1 1

Q8. Give A Circuit To Divide Frequency Of Clock Cycle By Two?

You can divide the frequency of a clock by way of simply imposing T Flip flop.

Give clock as clock input and tie the T input to logic 1.

Q9. Design A Divide-via-three Sequential Circuit With 50% Duty Circle?

Take a smiths counter with three f/f's this is to mention with 6 states(2*three) now double the i/p clock frequency to the counter the o/p of the 3rd f/f is divide through 6 of the i/p with 50% obligation cycle so efficiently u were given divide by way of three freq with 50% obligation cycle

Q10. How Do You Detect If Two eight-bit Signals Are Same?

XOR each bits of A with B (for eg A[0] xor B[0] ) and so forth. The o/p of eight xor gates are then given as i/p to an 8-i/p nor gate. If o/p is 1 then A=B.

Q11. What Are The Different Adder Circuits You Studied?

Adders are commonly of five sorts:

1) Ripple Carry Adder: The Ripple deliver adder(RCA) includes a constructing block named Half Adder(HA) that's cascaded to shape a Full Adder(FA). These building blocks HAs and FAs are also the constructing blocks of all types of adders.The n complete adders are cascaded to form n bit RCA.

The full adder has 3 input pins(enter Ai,input Bi,carryin Ci) and  output pins(Sum and Ci+1).Its equations are:

Sum=Ai^Bi^Ci

Ci+1=Ai.Bi+Bi.Ci+Ai.Ci

2)Carry Lookahead Adder: The Carry Lookahead Adder(CLA) reduces the delay as that during RCA. Let

Gi=Ai.Bi, and Pi=Ai^Bi, then Ci+1=Gi+Pi.Ci.

The expressions for Sum and Ci+1 is then defined absolutely in phrases of input pins as a substitute watch for enter bring to seem.

3)Carry Select Adder: The carry pick adder uses reproduction modules for every mixture of enter convey(i.E. 1 and 0).The multiplexers then pick out the right sum and bring output in line with the carry output of the previous levels.

Q12. What Are Set Up Time & Hold Time Constraints? What Do They Signify? Which One Is Critical For Estimating Maximum Clock Frequency Of A Circuit?

Suppose your turn-flop is tremendous aspect brought about. Time for which statistics need to be strong prior to high-quality aspect clock is called setup time constraint .

Time for which facts need to be stable after the advantageous edge of clock is called as maintain time constraint.

If any of these constraints are violated then turn-flop will input in meta strong state, wherein we cannot determine the output of flip-flop.

There are two equation:

Tcq + Tcomb> Tskew + Thold

Tcq + Tcomb<Tskew +T - Tsetup

Tcq is time delay when information enters the turn-flop and statistics comes at output of flip flop.

Tcomb is the good judgment put off among  flip flop.

Tskew is the postpone of clock to flip flop: assume there are two flip flop ,if clock reaches first to supply turn flop and then after some delay to vacation spot flip flop ,it's miles high quality skew and if vice versa then poor skew.

So in case you take 2 eq you'll see that setup time is the figuring out factor of clock's term.

Q13. Suppose You Have A Combinational Circuit Between Two Registers Driven By A Clock. What Will You Do If The Delay Of The Combinational Circuit Is Greater Than Your Clock Signal?

Use the concept of register-retiming.

Divide the full combinatorial postpone in two segments such that personally the postpone is much less the clock period.

This may be accomplished by means of putting a flip-flop within the combinational direction.

E.G,

clock length --- 5 ns

general cominational put off ---- 7

then divide the 7ns direction in two course of four or three (nice outcomes are obtained if delays are same for each path i.E three.5ns) via putting a flip-flop in between.

Q14. How Do You Detect A Sequence Of "1101" Arriving Serially From A Signal Line?

Sequence detector : A sequence detector offers an output of 1 on detecting the given sequence else the output is 0.

Ex : if the given sequence to be detected is 111

and input circulate is 1 1 0 1 1 1 zero zero 1 0 1 1 1 1 1

the output ought to be zero 0 0 0 0 1 0 zero zero 0 0 zero 1 1 1.

Soln: One of the distinct feasible methods to locate a series is the usage of a Mealy kind FSM.

Using the following table the State device can be designed. Because the number of bits within the sequence 1101 is 4 we've 4PS with the aid of the country

0 - 0 zero S2 zero S3/zero S3 eleven S4/0 S3/0

a hundred and ten S1/0 when in state S4 (PS),and input(X) from the sequence is 1,the sequence "1101" has been detected once and (to find the subsequent kingdom choose the longest "seq identified by a kingdom" column that fits a part of the sequence 1101--ie.,1 or 01 or one hundred and one ....)the NS is S2 since the series detected via the country S2 is 1(in 1101- 01 or a hundred and one ,and so on aren't present in the seq identified via the kingdom column ,)