Interview Questions.

Question 1. Why Does The Present Vlsi Circuits Use Mosfets Instead Of Bjts?

Answer :

Compared to BJTs, MOSFETs can be made very small as they occupy very small silicon vicinity on IC chip and are surprisingly easy in terms of manufacturing. Moreover digital and reminiscence ICs can be implemented with circuits that use only MOSFETs i.E. No resistors, diodes, and many others.

Question 2. What Are The Various Regions Of Operation Of Mosfet? How Are Those Regions Used?

Answer :

MOSFET has three regions of operation: the cut-off region, the triode place, and the saturation region.

The cut-off region and the triode location are used to function as switch. The saturation area is used to operate as amplifier.

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Question three. What Is Threshold Voltage?

Answer :

The price of voltage between Gate and Source i.E. VGS at which a sufficient number of mobile electrons gather within the channel vicinity to form a undertaking channel is called threshold voltage (Vt is high-quality for NMOS and poor for PMOS).

Question 4. What Does It Mean "the Channel Is Pinched Off"?

Answer :

For a MOSFET when VGS is more than Vt, a channel is induced. As we growth VDS modern-day starts offevolved flowing from Drain to Source (triode place). When we in addition boom VDS, until the voltage between gate and channel on the drain stop to come to be Vt, i.E. VGS - VDS = Vt, the channel intensity at Drain give up decreases nearly to 0, and the channel is said to be pinched off. This is where a MOSFET enters saturation area.

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Question 5. Explain The Three Regions Of Operation Of A Mosfet?

Answer :

Cut-off place: When VGS < Vt, no channel is induced and the MOSFET will be in cut-off region. No current flows.

Triode region: When VGS ≥ Vt, a channel will be induced and current starts flowing if VDS > 0. MOSFET may be in triode area as long as VDS < VGS - Vt.

Saturation region: When VGS ≥ Vt, and VDS ≥ VGS - Vt, the channel will be in saturation mode, where the current value saturates. There will be little or no effect on MOSFET when VDS is further increased.

Verilog Interview Questions
Question 6. What Is Channel-length Modulation?

Answer :

In practice, when VDS is further increased beyond saturation point, it does has some effect on the characteristics of the MOSFET. When VDS is increased the channel pinch-off point starts moving away from the Drain and towards the Source. Due to which the effective channel length decreases, and this phenomenon is called as Channel Length Modulation.

Question 7. Explain Depletion Region.

Answer :

When a positive voltage is applied across Gate, it causes the free holes (positive charge) to be repelled from the region of substrate under the Gate (the channel region). When these holes are pushed down the substrate they leave behind a carrier-depletion region.

Microprocessor Tutorial System Verilog Interview Questions
Question 8. What Is Body Effect?

Answer :

Usually, in an integrated circuit there will be several MOSFETs and in order to maintain cut-off condition for all MOSFETs the body substrate is connected to the most negative power supply (in case of PMOS most positive power supply). Which causes a reverse bias voltage between source and body that effects the transistor operation, by widening the depletion region. The widened depletion region will result in the reduction of channel depth. To restore the channel depth to its normal depth the VGS has to be increased. This is effectively seen as change in the threshold voltage - Vt. This effect, which is caused by applying some voltage to body is known as body effect.

Question 9. Give Various Factors On Which Threshold Voltage Depends?

Answer :

As discussed in the above question, the Vt depends on the voltage connected to the Body terminal. It also depends on the temperature, the magnitude of Vt decreases by about 2mV for every 1oC rise in temperature.

VHDL Interview Questions
Question 10. What Are The Steps Required To Solve Setup And Hold Violations In Vlsi?

Answer :

There are few steps that has to be performed to solved the setup and hold violations in VLSI. The steps are as follows:

The optimization and restructuring of the logic between the flops are carried way. This way the logics are combined and it helps in solving this problem.
There is way to modify the flip-flops that offer lesser setup delay and provide faster services to setup a device. Modifying the launch-flop to have a better hold on the clock pin, which provides CK->Q that makes the release-flop to be fast and helps in solving the setup violations.
The network of the clock can be changed to lessen the put off or slowing down of the clock that captures the motion of the turn-flop.
There may be delivered put off/buffer that lets in less put off to the characteristic that is used.
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Question eleven. What Are The Different Ways In Which Antenna Violation Can Be Prevented?

Answer :

Antenna violation happens in the course of the system of plasma etching in which the prices generating from one metallic strip to any other gets accumlated at a single location. The longer the strip the more the fees receives gathered. The prevention can be achieved through following technique:

Creating a strolling the metal line, that consists of atleast one metallic above the included layer.
There is a demand to jog the steel this is above the metallic getting the etching effect. This is because of the fact that if a steel gets the etching then the opposite steel receives disconnected if the prevention measures are not taken.
There is a manner to prevent it with the aid of including the opposite Diodes at the gates which are used within the circuits.
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Question 12. What Is The Function Of Tie-excessive And Tie-low Cells?

Answer :

Tie-excessive and tie-low are used to connect the transistors of the gate with the aid of using both the power or the ground. The gates are linked the use of the energy or ground then it could be became off and on due to the power jump from the ground. The cells are used to forestall the bouncing and smooth from of the contemporary from one mobile to some other. These cells are required Vdd that connects to the tie-excessive mobile as there may be a electricity deliver this is excessive and tie-low gets connected to Vss. This connection gets hooked up and the transistors characteristic properly with out the want of any ground bounce happening in any mobile.

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Question thirteen. What Is The Main Function Of Metastability In Vsdl?

Answer :

Metastability is an unknown kingdom that is given as neither one or zero. It is used in designing the device that violates the setup or hole time necessities. The setup time requirement want the statistics to be solid before the clock-part and the maintain time calls for the facts to be strong after the clock side has handed. There are potential violation that can lead to setup and hold violations as properly. The statistics that is produced in that is definitely asynchronous and clocked synchronous. This provide a manner to setup the nation thru which it may be regarded that the violations which can be occuring in the device and a right layout may be provided by way of using several different features.

Question 14. What Are The Steps Involved In Preventing The Metastability?

Answer :

Metastability is the unknown country and it prevents the violations using the subsequent steps:

right synchronizers are used that can be two degree or 3 stage whenever the statistics comes from the asynchronous domain. This helps in recovering the metastable country occasion.
The synchronizers are used in among move-clocking domain names. This reduces the metastability by doing away with the postpone this is due to the data detail which can be coming and taking time to get eliminated from the floor of steel.
Use of faster flip-flops that allow the transaction to be greater quicker and it removes the put off time among the only thing to another aspect. It uses a narrower metastable window that makes the delay manifest but quicker flip-flops help in making the procedure faster and reduce the time put off as properly.
Question 15. What Are The Different Design Constraints Occur In The Synthesis Phase?

Answer :

The steps that are concerned wherein the layout constraint occurs are:

first the advent of the clock with the frequency and the obligation cycle receives created. This clock enables in retaining the waft and synchronizing various devices which are used.
Define the transition time according the requirement on the input ports.
The load values are designated for the output ports that are mapped with the input ports.
Setting of the postpone values for each the input and output ports. The delay consists of the input and output put off.
Specify the case-settings to report the right time which are matched with the particular paths.
The clock uncertainty values are setup and preserve to show the violations which might be taking place.
Cmos Interview Questions
Question 16. What Are The Different Types Of Skews Used In Vlsi?

Answer :

There are three styles of skew which might be used in VLSI. The skew are used in clock to lessen the postpone or to apprehend the method as a consequence. The skew are as follows:

Local skew: This contain the distinction between the launching turn-flop and the destination flip-flop. This defines a time course between the two.

Global skew: Defines the difference among the earliest component reaching the turn glide and the the state-of-the-art arriving on the turn flow with the same clock domain. In this delays are not measured and the clock is furnished the same.

Useful skew: Defines the put off in capturing a turn flop paths that allows in putting in place the environment with unique requirement for the release and capture of the timing path. The maintain requirement in this example must be met for the layout reason.

Question 17. What Are The Changes That Are Provided To Meet Design Power Targets?

Answer :

To meet the layout power goal there have to be a process to layout with Multi-VDD designs, this area requires excessive performance, and additionally the high VDD that requires low-performance. This is used to create the voltage organization that allow the best level-shifter to shift and placed in move-voltage domains. There is a layout with the multiple threshold voltages that require high performance when the Vt will become low.

This have masses of contemporary leakage that makes the Vt mobile to lower the overall performance. The reduction can be completed in the leakage electricity because the clock on this devour greater electricity, so setting of an ultimate clock controls the module and allow it to receive extra energy. Clock tree permit the switching to take location while the clock buffers are utilized by the clock gating cells and decrease the switching by means of the energy reduction.

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Question 18. What Are The Different Measures That Are Required To Achieve The Design For Better Yield?

Answer :

To achieve higher yeild then there should be reduction in maufacturability flaws. The circuit perfomance has to be excessive that reduces the parametric yield. This discount is because of method versions The measures that may be taken are:

Creation of effective runset documents that consists of spacing and shorting guidelines. This also includes all of the permissions that has to accept to the user.
Check the areas in which the design is having lithographic issues, that includes sharp cuts.
Use of redundant vias to lessen the breakage of the modern-day and the barrier.
Optimal placing of the de-coupling capacitances can be done so that there's a discount in power-surges.
Verilog Interview Questions
Question 19. What Is The Difference Between The Mealy And Moore State Machine?

Answer :

Moore model includes the device that have an access action and the output depends most effective at the kingdom of the system, while mealy model most effective uses Input Actions and the output depends at the nation and additionally on the previous inputs which can be provided at some point of this system.
Moore fashions are used to layout the hardware structures, while each hardware and software program systems may be designed the use of the mealy version.
Mealy device's output rely upon the country and enter, whereas the output of the moore device relies upon simplest on the kingdom because the application is written within the nation only.
Mealy gadget is having the output via the aggregate of both input and the country and the trade the state of kingdom variables also have a few delay while the exchange in the sign takes area, whereas in Moore system does not have system defects and its ouput is dependent only on states not at the enter signal degree.
Question 20. What Is The Difference Between Synchronous And Asynchronous Reset?

Answer :

Synchronous reset is the common sense in an effort to synthesize to smaller turn-flops. In this the clock works as a clear out imparting the small reset system defects but the system defects occur on the energetic clock area, whereas the asynchronous reset is also called reset release or reset removal. The clothier is responsible of brought the reset to the facts paths.
The synchronous reset is used for all the sorts of design that are used to filter out the common sense system defects provided among the clocks. Whereas, the circuit may be reset with or without the clock gift.
Synchronous reset does not allow the synthesis device for use without difficulty and it distinguishes the reset sign from other information signal. The launch of the reset can arise simplest while the clock is having its initial duration. If the discharge takes place close to the clock side then the turn-flops can be metastable.
FPGA Interview Questions
Question 21. What Are The Different Design Techniques Required To Create A Layout For Digital Circuits?

Answer :

The special design techniques to create the Layout for virtual circuits are as follows:

Digital layout consists of the standard cells and constitute the peak this is required for the format. The format relies upon on the scale of the transistor. It additionally includes the specification for Vdd and GND steel paths that must be maintained uniformly.
Use of metal in a single course only to apply the metal directly. The metal can be used and displayed in any path.
Placing of the substrate that region wherein it indicates all of the empty spaces of the format wherein there's resistances.
Use of fingered transistors permits the design to be more smooth and it is straightforward to preserve a symmetry as well.
Question 22. Write A Program To Explain The Comparator?

Answer :

To make a comparator there's a requirement to apply multiplexer this is having one input and plenty of outputs. This permits the selecting of the most numbers which can be required to design the comparator. The implementation of the two bit comparator may be performed using the law of tigotomy that states that A > B, A < B, A = B (Law of trigotomy). The comparator can be implemented using:

combinational logic circuits or multiplexers that uses the HDL language to write the schematic at RTL and gate level.

Behavioral model of comparator represented like:

module comp0 (y1,y2,y3,a,b);
input [1:0] a,b;
output y1,y2,y3;
wire y1,y2,y3;
assign y1= (a >b)? 1:0;
assign y2= (b >a)? 1:0;
assign y3= (a==b)? 1:zero;
endmodule

Question 23. What Is The Function Of Chain Reordering?

Answer :

The optimization technique that is used makes it tough for the chain ordering machine to direction because of the congestion caused by the placement of the cells. There are device available that automate the reordering of the chain to reduce the congestion this is produced at the first level. It increases the hassle of the chain gadget and this additionally allow the overcoming of the buffers that need to be inserted into the test path.

The boom of the preserve time within the chain reordering can cause brilliant amount of delay. Chain reordering lets in the cellular to be come within the ordered layout whilst the usage of the one of a kind clock domain names. It is used to lessen the time delay caused by random technology of the detail and the placement of it.

ASIC Interview Questions
Question 24. What Are The Steps Involved In Designing An Optimal Pad Ring?

Answer :

To make the layout for an top of the line pad ring there is a requirement for the nook-pads that comes throughout all the corners of the pad-ring. It is used to provide power continuity and maintain the resistance low.
It calls for the pad ring this is to fulfil the energy domain names that is commonplace for all of the ground throughout all of the domains.
It requires the pad ring to include simultaneous switching noise gadget that place the switch cell pads in pass energy domains for distinctive pad duration.
Drive electricity is been seen to check the modern-day necessities and the timings to make the power pads.
Choose a no-connection pad that is used to fill the pad-frame whilst there may be no requirement for the inputs to receive. This consumes much less energy while there's no input given at a particular time.
Checking of the oscillators pads take region that makes use of the synchronous circuits to make the clock statistics synchronize with the prevailing one.
System Verilog Interview Questions
Question 25. What Is The Function Of Enhancement Mode Transistor?

Answer :

The enhancement mode transistors are also called as discipline impact transistors as they depend upon the electric filed to manipulate the form and conductivity of the channel. This includes one sort of price provider in a semiconductor cloth environment. This also uses the unipolar transistors to distinguish themselves with the unmarried-provider kind operation transistors that consists of the bipolar junction transistor.

The uses of subject impact transistor is to bodily implementation of the semiconductor substances this is in comparison with the bipolar transistors. It gives with the general public of the charge carrier devices. The gadgets that consists of energetic channels to make the fee vendors skip thru. It consists of the idea of drain and the source.

Question 26. What Is The Purpose Of Having Depletion Mode Device?

Answer :

Depletion modes are used in MOSFET it is a tool that stays ON at 0 gate-source voltage. This tool consists of load resistors which can be used within the good judgment circuits. This sorts are utilized in N-kind depletion-load devices that permit the edge voltages to be taken and use of -3 V to +3V is done.

The drain is more effective on this contrast of PMOS where the polarities receives reversed. The mode is generally determined by way of the signal of threshold voltage for N-kind channel. Depletion mode is the fine one and used in lots of technology to symbolize the real good judgment circuit. It defines the logic own family this is depending on the silicon VLSI. This includes pull-down switches and hundreds for pull-ups.

BIOS Interview Questions
Question 27. What Is The Difference Between Nmos And Pmos Technologies?

Answer :

PMOS includes steel oxide semiconductor this is made at the n-type substrates and consists of active careers named as holes. These holes are used for migration purpose of the prices between the p-kind and the drain. Whereas, NMOS includes the metal oxide semiconductor and they're made on p-kind substrates. It consists of electrons as their companies and migration happens between the n-type supply and drain.
On applying the high voltage at the common sense gates NMOS may be conducted and will get activated, whereas PMOS require low voltage to be activated.
NMOS are quicker than PMOS as the vendors that NMOS makes use of are electrons that travels faster than holes. The velocity is twice as rapid as holes.
PMOS are more proof against noice than NMOS.
VHDL Interview Questions
Question 28. What Is The Difference Between Cmos And Bipolar Technologies?

Answer :

CMOS technology allows the strength dissipation to be low and it gives greater power output, while bipolar takes plenty of strength to run the gadget and the ciricutary require masses of energy to get activated.
CMOS generation affords excessive input impedance this is low pressure modern that allow more present day to be flown in the cirucit and preserve the circuit in an awesome function, whereas it affords high force present day approach extra input impedance.
CMOS generation gives scalable threshold voltage greater in comparison to the Bipolar generation that provides low threshold voltage.
CMOS generation affords excessive noise margin, packing density while Bipolory generation lets in to have low noise margin in order that to reduce the high volues and provide low packing density of the components.
Question 29. What Are The Different Classification Of The Timing Control?

Answer :

There are special class wherein the timing manipulate facts is split and they're:

Delay based totally timing manipulate: that is primarily based on timing control that lets in to manage the factor such that the delay can be notified and anyplace it is required it could accept. The delays which are primarily based in this are as:

- Regular delay manipulate: that controls the delay at the regular foundation.
- Intra-undertaking delay manipulate: that controls the internal delays.
- Zero put off manipulate

Events based totally timing manage: this is based totally on the occasions which can be completed when an event happens or a trigger is ready on an event that takes location. It consists of

- Regular event manipulate
- Named event control
- Event OR manage

Level touchy timing manipulate: that is primarily based on the ranges which can be given like 0 level or 1 stage this is being given or shown and the data is being modified according the levels which might be being set. When a stage changes the timing manipulate additionally changes.
Microprocessor Interview Questions
Question 30. We Have Multiple Instances In Rtl(sign in Transfer Language), Do You Do Anything Special During Synthesis Stage?

Answer :

While writing RTL(Register Transfer language),say in verilog or in VHDL language, we dont write the equal module functionality time and again, we use a idea known as as instantiation, where in as in line with the language, the instanciation of a module will behave just like the figure module in terms of capability, where at some point of synthesis stage we want the total code so that the synthesis device can have a look at the good judgment , structure and map it to the library cells, so we use a command in synthesis , referred to as as "UNIQUIFY" in an effort to update the instantiations with the real common sense, due to the fact as soon as we're in a synthesis levels we need to visualize as actual cells and no extra modelling just for capability alone, we need to visualize in-terms of physical international as properly. 

Question 31. What Is Tie-excessive And Tie-low Cells And Where It Is Used?

Answer :

Tie-high and Tie-Low cells are used to connect the gate of the transistor to either electricity or floor. In deep sub micron methods, if the gate is connected to energy/floor the transistor is probably grew to become on/off because of electricity or floor bounce. The proposal from foundry is to apply tie cells for this reason. These cells are part of trendy-mobile library. The cells which require Vdd, comes and connect to Tie excessive...(so tie high is a strength supply cellular)...Whilst the cells which wishes Vss connects itself to Tie-low.

Question 32. What Is The Difference Between Latches And Flip-flops Based Designs?

Answer :

Latches are level-sensitive and flip-flops are side touchy. Latch based totally layout and flop based totally design is that latch allowes time borrowing which a culture flop does no longer. That makes latch based totally design more efficient. But at the same time, latch based totally layout is greater complicated and has extra problems in min timing (races). Its STA with time borrowing in deep pipelining may be quite complex.

VLSI Design Interview Questions
Question 33. What Is Local-skew, Global-skew,beneficial-skew Mean?

Answer :

Local skew : The distinction among the clock attaining on the launching flop vs the clock achieving the vacation spot turn-flop of a timing-direction.

Global skew : The distinction among the earliest attaining flip-flop and brand new accomplishing turn-flop for a same clock-domain.

Useful skew: Useful skew is a concept of delaying the shooting turn-flop clock direction, this technique allows in meeting setup requirement with in the launch and seize timing path. But the maintain-requirement has to be met for the design.

8051 Microcontroller Interview Questions