Top 100+ Vlsi Design Interview Questions And Answers
Question 1. What Are Four Generations Of Integration Circuits?
Answer :
SSI (Small Scale Integration)
MSI (Medium Scale Integration)
LSI (Large Scale Integration)
VLSI (Very Large Scale Integration)
Question 2. Give The Advantages Of Ic?
Answer :
Size is much less
High Speed
Less Power Dissipation
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Question three. Give The Variety Of Integrated Circuits?
Answer :
More Specialized Circuits
Application Specific Integrated Circuits (ASICs)
Systems-On-Chips
Question four. Give The Basic Process For Ic Fabrication?
Answer :
Silicon wafer Preparation
Epitaxial Growth
Oxidation
Photolithography
Diffusion
Ion Implantation
Isolation approach
Metallization
Assembly processing & Packaging
Perl Scripting Tutorial
Question 5. What Are The Various Silicon Wafer Preparation?
Answer :
Crystal boom & doping
Ingot trimming & grinding
Ingot cutting
Wafer polishing & etching
Wafer cleansing.
Digital Electronics Interview Questions
Question 6. Different Types Of Oxidation?
Answer :
Dry & Wet Oxidation
Question 7. What Is The Transistors Cmos Technology Provides?
Answer :
N-kind transistors & p-kind transistors.
Digital Communication Tutorial Verilog Interview Questions
Question eight. What Are The Different Layers In Mos Transistors?
Answer :
Drain, Source & Gate
Question nine. What Is Enhancement Mode Transistor?
Answer :
The device that is typically reduce-off with zero gate bias.
System Verilog Interview Questions
Question 10. What Is Depletion Mode Device?
Answer :
The Device that conduct with zero gate bias.
Question eleven. When The Channel Is Said To Be Pinched – Off?
Answer :
If a large Vds is applied this voltage with deplete the Inversion layer. This Voltage correctly pinches off the channel near the drain.
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Question 12. Give The Different Types Of Cmos Process?
Answer :
p-properly system
n-properly process
Silicon-On-Insulator Process
Twin- bath Process
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Question 13. What Are The Steps Involved In Twin-bathtub Process?
Answer :
Tub Formation
Thin-oxide Construction
Source & Drain Implantation
Contact cut definition
Metallization.
Question 14. What Are The Advantages Of Silicon-on-insulator Process?
Answer :
No Latch-up.
Due to absence of bulks transistor systems are denser than bulk silicon.
Question 15. What Is Bicmos Technology?
Answer :
It is the mixture of bipolar generation & CMOS era.
Physical Design Engineer Interview Questions
Question 16. What Are The Basic Processing Steps Involved In Bicmos Process?
Answer :
Additional mask defining P base region:
N Collector place
Buried Sub collector (SCCD)
Processing steps in CMOS technique
Question 17. What Are The Advantages Of Cmos Process?
Answer :
Low strength Dissipation
High Packing density
Bi directional capability
Cmos Interview Questions
Question 18. What Is The Fundamental Goal In Device Modeling?
Answer :
To gain the purposeful courting a few of the terminal electrical variables of the device this is to be modeled.
Digital Electronics Interview Questions
Question 19. Define Short Channel Devices?
Answer :
Transistors with Channel period less than 3- 5 microns are termed as Short channel devices. With quick channel devices the ratio among the lateral & vertical dimensions are decreased.
Question 20. What Is Pulling Down Device?
Answer :
A tool related in order to tug the output voltage to the lower deliver voltage commonly 0V is called pull down device.
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Question 21. What Is Pulling Up Device?
Answer :
A tool linked so as to tug the output voltage to the top supply voltage usually VDD is known as pull up device.
Question 22. Why Nmos Technology Is Preferred More Than Pmos Technology?
Answer :
N- Channel transistors has extra switching speed while as compared tp PMOS transistors.
Question 23. What Are The Different Operating Regions Foes An Mos Transistor?
Answer :
Cutoff location
Non- Saturated Region
Saturated Region
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Question 24. What Are The Different Mos Layers?
Answer :
N-diffusion
P-diffusion
Polysilicon
Metal
Verilog Interview Questions
Question 25. What Is Stick Diagram?
Answer :
It is used to deliver data through the use of coloration code. Also it is the caricature of a chip layout.
Question 26. What Are The Uses Of Stick Diagram?
Answer :
It can be drawn plenty easier and quicker than a complex layout.
These are specifically vital gear for format built from big cells.
Question 27. Give The Various Color Coding Used In Stick Diagram?
Answer :
Green – n-diffusion
Red- Polysilicon
Blue –metallic
Yellow- implant
Black-touch areas.
System Verilog Interview Questions
Question 28. Compare Between Cmos And Bipolar Technologies?
Answer :
CMOS Technology:
Low static energy dissipation. High input impedance (low drive modern-day). Scalable threshold voltage. High noise margin. High packing density. High delay sensitivity to load (fanout boundaries). Low output power current. Low gm (gm a VIN). Bidirectional capability. A near perfect switching tool
Bipolar era:
High energy dissipation. Low enter impedance (excessive force modern). Low voltage swing common sense. Low packing density. Low postpone sensitivity to load. High output pressure modern-day. High gm (gm an eVin). High ft at low cutting-edge. Essentially unidirectional.
Question 29. Define Threshold Voltage In Cmos?
Answer :
The Threshold voltage, VT for a MOS transistor can be defined because the voltage implemented between the gate and the source of the MOS transistor underneath which the drain to supply contemporary, IDS efficaciously drops to zero.
Question 30. What Is Body Effect?
Answer :
The threshold voltage VT isn't always a regular w. R. To the voltage difference between the substrate and the supply of MOS transistor. This impact is referred to as substrate-bias effect or body impact.
Question 31. What Is Channel-length Modulation?
Answer :
The modern-day among drain and supply terminals is steady and independent of the carried out voltage over the terminals. This isn't always absolutely accurate. The powerful duration of the conductive channel is absolutely modulated through the applied VDS, growing VDS reasons the depletion vicinity at the drain junction to develop, decreasing the duration of the effective channel.
Question 32. What Is Latch – Up?
Answer :
Latch up is a condition in which the parasitic components supply upward thrust to the status quo of low resistance engaging in paths between VDD and VSS with disastrous outcomes. Careful control all through fabrication is necessary to avoid this hassle.
Question 33. Define Rise Time?
Answer :
Rise time, tr is the time taken for a waveform to rise from 10% to ninety% of its constant-state cost.
VHDL Interview Questions
Question 34. Define Fall Time?
Answer :
Fall time, tf is the time taken for a waveform to fall from ninety% to ten% of its regular-country price.
Question 35. Define Delay Time?
Answer :
Delay time, td is the time distinction between enter transition (50%) and the 50% output level. This is the time taken for a common sense transition to pass from input to output.
Question 36. What Are Two Components Of Power Dissipation?
Answer :
There are additives that establish the amount of energy dissipated in a CMOS circuit.
These are:
Static dissipation due to leakage current or different cutting-edge drawn constantly from the electricity deliver.
Dynamic dissipation due to.
Switching temporary contemporary.
Charging and discharging of load capacitances.
Physical Design Engineer Interview Questions
Question 37. Give Some Of The Important Cad Tools?
Answer :
Some of the critical CAD equipment are:
Layout editors
Design Rule checkers (DRC)
Circuit extraction
Question 38. What Is Verilog?
Answer :
Verilog is a widespread motive hardware descriptor language. It is similar in syntax to the C programming language. It can be used to model a digital system at many stages of abstraction ranging from the algorithmic degree to the transfer degree.
Question 39. What Are The Various Modeling Used In Verilog?
Answer :
Gate-level modeling
Data-drift modeling
Switch-level modeling
Behavioral modeling
Question forty. What Is The Structural Gate-level Modeling?
Answer :
Structural modeling describes a virtual good judgment networks in terms of the additives that make up the machine. Gate-degree modeling is primarily based on the usage of primitive common sense gates and specifying how they may be wired together.
Cmos Interview Questions
Question forty one. What Is Switch-degree Modeling?
Answer :
Verilog lets in switch-degree modeling that is based at the conduct of MOSFETs. Digital circuits on the MOS-transistor degree are described using the MOSFET switches.
Question 42. What Are Identifiers?
Answer :
Identifiers are names of modules, variables and other objects that we are able to reference within the design. Identifiers consists of upper and decrease case letters, digits zero thru 9, the underscore individual(_) and the dollar signal($). It have to be a single group of characters. Examples: A014, a, b, in_o, s_out.
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Question forty three. What Are The Value Sets In Verilog?
Answer :
Verilog supports four levels for the values had to describe hardware called value sets.
Value degrees Condition in hardware circuits:
zero Logic 0, fake condition
1 Logic one, actual situation
X Unknown logic fee
Z High impedance, floating state
Question forty four. What Are The Types Of Gate Arrays In Asic?
Answer :
Channeled gate arrays
Channel less gate arrays
Structured gate arrays
Question 45. Give The Classifications Of Timing Control?
Answer :
Methods of timing manage:
Delay-primarily based timing control
Event-primarily based timing manipulate
Level-sensitive timing manipulate
Types of delay-based timing manipulate:
Regular postpone control
Intra-mission delay manage
Zero postpone manipulate
Types of occasion-based timing manage:
Regular occasion control
Named occasion manage
Event OR control
Level-touchy timing manage
Question forty six. What Are Gate Primitives?
Answer :
Verilog helps simple good judgment gates as predefined primitives. Primitive logic function keyword gives the basics for structural modeling at gate level. These primitives are instantiated like modules except that they are predefined in verilog and do not want a module definition. The critical operations are and, nand, or, xor, xnor, and buf (non-inverting force buffer).
Question forty seven. Give The Two Blocks In Behavioral Modeling?
Answer :
An initial block executes once inside the simulation and is used to installation preliminary situations and step-by-step records waft.
An always block executes in a loop and repeats throughout the simulation.
Question forty eight. What Are The Types Of Conditional Statements?
Answer :
No else assertion:
Syntax: if ([expression]) proper – statement;
One else assertion:
Syntax: if ([expression]) proper – statement; else fake-assertion;
Nested if-else-if:
Syntax:
if ([expression1]) proper statement 1;
else if ([expression2]) true-statement 2;
else if ([expression3]) true-statement 3;
else default-statement;
The [expression] is evaluated. If it is actual (1 or a non-zero fee) authentic-assertion is finished. If it's far false (0) or ambiguous (x), the false-assertion is carried out.
Question forty nine. Name The Types Of Ports In Verilog?
Answer :
Input port Input
Output port Output
Bidirectional port inout
Question 50. What Are The Types Of Procedural Assignments?
Answer :
Blocking project
Non-blockading mission
Question 51. Give The Different Types Of Asic?
Answer :
1. Full custom ASICs
2. Semi-custom ASICs:
Standard cell based totally ASICs.
Gate-array based totally ASICs.
Three. Programmable ASICs:
Programmable Logic Device (PLD).
Field Programmable Gate Array (FPGA).
Question fifty two. What Is The Full Custom Asic Design?
Answer :
In a complete custom ASIC, an engineer designs a few or all of the common sense cells, circuits or layout in particular for one ASIC. It makes feel to take this technique best if there are no appropriate existing cellular libraries available that can be used for the entire design.
Question 53. What Is The Standard Cell-primarily based Asic Design?
Answer :
A cell-primarily based ASIC (CBIC) makes use of predesigned logic cells called widespread cells. The wellknown cellular areas additionally known as fle4xible blocks in a CBIC are built of rows of trendy cells. The ASIC fashion designer defines only the position of preferred cells and the interconnect in a CBIC. All the masks layers of a CBIC are customized and are particular to a particular patron.
Question 54. Differentiate Between Channeled & Channel Less Gate Array?
Answer :
Channeled Gate Array: Only the interconnect is customized. The interconnect uses predefined areas between rows of base cells. Routing is accomplished the usage of the areas. Logic density is much less
Channel much less Gate Array: Only the top few mask layers are customized. No predefined areas are set aside for routing between cells. Routing is performed using the area of transistors unused. Logic density is better.
Question fifty five. Give The Constituent Of I/o Cell In 22v10?
Answer :
2V10 I/O cell includes:
A check in
An output four:1 mux
A tristate buffer
A 2:1 enter mux
It has the following characteristics:
12 inputs
10 I/Os
Product time nine 10 12 14 sixteen 14 12 10 8
24 pins
Question fifty six. What Is A Fpga?
Answer :
A subject programmable gate array (FPGA) is a programmable logic tool that helps implementation of incredibly big logic circuits. FPGAs may be used to put in force a common sense circuit with greater than 20,000 gates whereas a CPLD can put in force circuits of upto approximately 20,000 equal gates.
Question fifty seven. What Are The Different Methods Of Programming Of Pals?
Answer :
The programming of PALs is performed in three most important methods:
Fusible hyperlinks
UV – erasable EPROM
EEPROM (EePROM) – Electrically Erasable Programmable ROM
Question 58. What Is An Antifuse?
Answer :
An antifuse is usually high resistance (>100MW). On software of suitable programming voltages, the antifuse is changed permanently to a low-resistance structure (two hundred-500W).
Question 59. What Are The Different Levels Of Design Abstraction At Physical Design?
Answer :
Architectural or functional degree
Register Transfer-degree (RTL)
Logic stage
Circuit degree
Question 60. What Are Macros?
Answer :
The logic cells in a gate-array library are frequently referred to as macros.
Question 61. What Is Programmable Interconnects?
Answer :
In a PAL, the device is programmed by means of converting the characteristics if the switching detail. An alternative could be to application the routing.
Question 62. Give The Steps In Asic Design Flow?
Answer :
Design entry
Logic synthesis System partitioning
Pre format simulation.
Floor making plans
Placement
Routing
Extraction
Post format simulation
Question sixty three. Mention The Levels At Which Testing Of A Chip Can Be Done?
Answer :
At the wafer stage
At the packaged-chip stage
At the board degree
At the gadget stage
In the sphere
Question 64. What Are The Categories Of Testing?
Answer :
Functionality assessments
Manufacturing exams
Question 65. Write Notes On Functionality Tests?
Answer :
Functionality assessments affirm that the chip performs its intended function. These checks assert that all the gates inside the chip, acting in live performance, reap a desired characteristic. These checks are typically used early within the layout cycle to verify the capability of the circuit.
Question 66. Write Notes On Manufacturing Tests?
Answer :
Manufacturing checks confirm that each gate and check in in the chip features efficaciously. These checks are used after the chip is manufactured to confirm that the silicon is intact.
Question sixty seven. Mention The Defects That Occur In A Chip?
Answer :
Layer-to-layer shorts
Discontinuous wires
Thin-oxide shorts to substrate or properly
Question 68. Give Some Circuit Maladies To Overcome The Defects?
Answer :
Nodes shorted to electricity or floor
Nodes shorted to every different
Inputs floating/outputs disconnected
Question sixty nine. What Are The Tests For I/o Integrity?
Answer :
I/O stage check
Speed test
IDD take a look at
Question 70. What Is Meant By Fault Models?
Answer :
Fault version is a model for a way faults occur and their impact on circuits.
Question seventy one. Give Some Examples Of Fault Models?
Answer :
Stuck-At Faults.
Short-Circuit and Open-Circuit Faults.
Question seventy two. What Is Stuck – At Fault?
Answer :
With this model, a faulty gate input is modeled as a “stuck at zero” or “caught at one”. These faults most regularly occur because of thin -oxide shorts or metallic-to-steel shorts.
Question seventy three. What Is Meant By Observability?
Answer :
The observability of a selected internal circuit node is the degree to which you can actually have a look at that node at the outputs of an integrated circuit.
Question seventy four. What Is Meant By Controllability?
Answer :
The controllability of an internal circuit node within a chip is a measure of the ease of putting the node to at least one or 0 states.
Question 75. What Is Known As Percentage-fault Coverage?
Answer :
The general number of nodes that, when set to one or 0, do result in the detection of the fault, divided with the aid of the whole wide variety of nodes in the circuit, is referred to as the proportion-fault insurance.
Question 76. What Is Fault Grading?
Answer :
Fault grading includes two steps. First, the node to be faulted is selected. A simulation is administered with out a faults inserted, and the outcomes of this simulation are stored. Each node or line to be faulted is set to 0 and then 1 and the take a look at vector set is implemented. If and when a discrepancy is detected among the faulted circuit reaction and the best circuit response, the fault is stated to be detected and the simulation is stopped.
Question seventy seven. Mention The Ideas To Increase The Speed Of Fault Simulation?
Answer :
Parallel simulation
Concurrent simulation
Question seventy eight. What Is Fault Sampling?
Answer :
An method to fault evaluation is called fault sampling. This is used in circuits in which it's far not possible to fault each node in the circuit. Nodes are randomly decided on and faulted. The ensuing fault detection rate may be statistically inferred from the number of faults that are detected in the fault set and the size of the set. The randomly selected faults are independent. It will determine whether the fault insurance exceeds a favored stage.
Question seventy nine. What Are The Approaches In Design For Test Ability?
Answer :
Ad hoc testing
Scan-primarily based procedures
Self-check and built-in testing
Question 80. Mention The Common Techniques Involved In Ad Hoc Testing?
Answer :
Partitioning large sequential circuits
Adding test factors
Adding multiplexers
Providing for easy state reset
Question eighty one. What Are The Scan-based Test Techniques?
Answer :
Level sensitive scan design
Serial experiment
Partial serial scan
Parallel scan
Question eighty two. What Are The Two Tenets In Lssd?
Answer :
The circuit is level-touchy. Each sign in can be converted to a serial shift register.
Question 83. What Are The Self-check Techniques?
Answer :
Signature analysis and BILBO
Memory self-check
Iterative common sense array checking out
Question eighty four. What Is Known As Bilbo?
Answer :
Signature evaluation may be merged with the test approach to create a structure referred to as BILBO- for Built in Logic Block Observation.
Question 85. What Is Known As Iddq Testing?
Answer :
A famous method of trying out for bridging faults is referred to as IDDQ or contemporary deliver monitoring. This relies at the truth that when a complementary CMOS logic gate isn't always switching, it draws no DC modern. When a bridging fault takes place, for some combination of input situations a measurable DC IDD will float.
Question 86. What Are The Applications Of Chip Level Test Techniques?
Answer :
Regular good judgment arrays
Memories
Random logic
Question 87. What Is Boundary Scan?
Answer :
The growing complexity of forums and the movement to technology like multichip modules and surface-mount technologies ended in machine designers agreeing on a unified experiment-based totally methodology for trying out chips on the board. This is known as boundary test.
Question 88. What Is The Test Access Port?
Answer :
The Test Access Port (TAP) is a definition of the interface that wishes to be covered in an IC to make it able to being blanketed in boundary-scan architecture.
The port has four or five single bit connections, as follows:
TCK (The Test Clock Input)
TMS (The Test Mode Select)
TDI (The Test Data Input)
TDO (The Test Data Output)
It additionally has an elective sign:
TRST*(The Test Reset Signal)
Question 89. What Are The Contents Of The Test Architecture?
Answer :
The take a look at structure consists of:
The TAP interface pins
A set of test-data registers
An education check in
A TAP controller
Question 90. What Is The Tap Controller?
Answer :
The TAP controller is a 16-nation FSM that proceeds from country to nation primarily based on the TCK and TMS indicators. It gives signals that manage the take a look at statistics registers, and the training sign in. These consist of serial-shift clocks and replace clocks.
Question 91. What Is Known As Test Data Register?
Answer :
The test-information registers are used to set the inputs of modules to be tested, and to acquire the outcomes of running assessments.
Question ninety two. What Is Known As Boundary Scan Register?
Answer :
The boundary scan sign in is a special case of a information check in. It allows circuit-board interconnections to be examined, external components examined, and the nation of chip virtual I/Os to be sampled.
