Top 100+ Verilog Interview Questions And Answers
Question 1. Write A Verilog Code To Swap Contents Of Two Registers With And Without A Temporary Register?
Answer :
With temp reg ;
usually @ (posedge clock)
begin
temp=b;
b=a;
a=temp;
end
Without temp reg;
constantly @ (posedge clock)
begin
a <= b;
b <= a;
give up
Question 2. Difference Between Task And Function?
Answer :
Function:
A feature is unable to allow a mission however functions can permit different functions.
A function will carry out its required obligation in zero simulation time. ( The software time will no longer be incremented for the duration of the characteristic ordinary)
Within a characteristic, no event, delay or timing manage statements are permitted
In the invocation of a feature their should be as a minimum one argument to be handed.
Functions will most effective go back a unmarried fee and cannot use either output or inout statements.
Tasks:
Tasks are able to permitting a feature in addition to enabling different versions of a Task
Tasks additionally run with a 0 simulation but they could if required be finished in a non zero simulation time.
Tasks are allowed to contain any of those statements.
A venture is permitted to apply 0 or more arguments that are of type output, enter or inout.
A Task is unable to return a fee but has the power to pass a couple of values through the output and inout statements .
Perl Scripting Interview Questions
Question three. Difference Between Inter Statement And Intra Statement Delay?
Answer :
//define sign up variables
reg a, b, c;
//intra challenge delays
initial
start
a = 0; c = zero;
b = #five a + c; //Take value of a and c at the time=0, evaluate
//a + c and then wait 5 time gadgets to assign fee
//to b.
Stop
//Equivalent technique with brief variables and regular delay control
preliminary
begin
a = 0; c = zero;
temp_ac = a + c;
#five b = temp_ac; //Take price of a + c on the cutting-edge time and
//save it in a brief variable. Even though a and c
//may trade among 0 and five,
//the value assigned to b at time five is unaffected.
Stop
Question four. Difference Between $screen,$display & $strobe?
Answer :
These commands have the same syntax, and display textual content on the display all through simulation. They are a whole lot less handy than waveform show tools like cwaves?. $display and $strobe show as soon as whenever they may be carried out, while $reveal shows every time one in every of its parameters changes.
The difference among $display and $strobe is that $strobe presentations the parameters at the very cease of the modern simulation time unit instead of precisely wherein it is accomplished. The format string is like that in C/C++, and may comprise format characters. Format characters include %d (decimal), %h (hexadecimal), %b (binary), %c (man or woman), %s (string) and %t (time), %m (hierarchy stage). %5d, %5b and so forth. Might give exactly five spaces for the variety instead of the distance wished. Append b, h, o to the task name to change default layout to binary, octal or hexadecimal.
Syntax:
$show (“format_string”, par_1, par_2, ... );
$strobe (“format_string”, par_1, par_2, ... );
$screen (“format_string”, par_1, par_2, ... );
Perl Scripting Tutorial
Question five. What Is Difference Between Verilog Full Case And Parallel Case?
Answer :
A "complete" case statement is a case declaration in which all feasible case-expression binary patterns can be matched to a case object or to a case default. If a case statement does now not include a case default and if it is viable to find a binary case expression that does not in shape any of the described case objects, the case declaration isn't "full."
A "parallel" case declaration is a case assertion wherein it's miles best possible to fit a case expression to 1 and simplest one case object. If it's far viable to find a case expression that would healthy more than one case object, the matching case items are known as "overlapping" case objects and the case declaration isn't "parallel."
Shell Scripting Interview Questions
Question 6. What Is Meant By Inferring Latches,how To Avoid It?
Answer :
Consider the subsequent :
always @(s1 or s0 or i0 or i1 or i2 or i3)
case (s1, s0)
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
endcase
in a case statement if all the possible combinations aren't as compared and default is also not special like in instance above a latch will be inferred ,a latch is inferred because to reproduce the preceding price when unknown branch is targeted.
For instance in above case if s1,s0=3 , the previous stored fee is reproduced for this storing a latch is inferred.
The identical may be found in IF announcement in case an ELSE IF isn't distinctive.
To keep away from inferring latches make sure that every one the instances are mentioned if not default condition is furnished.
Question 7. Tell Me How Blocking And Non Blocking Statements Get Executed?
Answer :
Execution of blockading assignments can be regarded as a one-step technique:
1. Evaluate the RHS (right-hand facet equation) and update the LHS (left-hand aspect expression) of the blockading assignment without interruption from every other Verilog assertion. A blockading challenge "blocks" trailing assignments within the same constantly block from taking place until after the modern-day mission has been completed
Execution of nonblocking assignments can be regarded as a two-step process:
Evaluate the RHS of nonblocking statements at the start of the time step.
Update the LHS of nonblocking statements on the stop of the time step.
Shell Scripting Tutorial System Administration Interview Questions
Question 8. Variable And Signal Which Will Be Updated First?
Answer :
Signals
Question 9. What Is Sensitivity List?
Answer :
The sensitivity listing indicates that once a trade happens to any individual of factors within the list alternate, start…cease assertion inside that usually block gets performed.
System Verilog Interview Questions
Question 10. In A Pure Combinational Circuit Is It Necessary To Mention All The Inputs In Sensitivity Disk? If Yes, Why?
Answer :
Yes in a pure combinational circuit is it important to mention all of the inputs in sensitivity disk other clever it will result in pre and post synthesis mismatch.
VLSI Design Tutorial
Question 11. Tell Me Structure Of Verilog Code You Follow?
Answer :
A right template in your Verilog document is shown underneath.
// timescale directive tells the simulator the bottom gadgets and precision of the simulation
`timescale 1 ns / 10 playstation
module call (input and outputs);
// parameter declarations
parameter parameter_name = parameter price;
// Input output declarations
input in1;
enter in2; // single bit inputs
output [msb:lsb] out; // a bus output
// internal sign sign up kind declaration - register kinds (most effective assigned inside usually statements). Reg register
variable 1;
reg [msb:lsb] sign in variable 2;
// internal signal. Internet type assertion - (most effective assigned outdoor always statements) twine internet variable 1;
// hierarchy - instantiating another module
reference call instance name (
.Pin1 (net1),
.Pin2 (net2),
.
.Pinn (netn)
);
// synchronous approaches
usually @ (posedge clock)
begin
.
End
// combinatinal methods
usually @ (signal1 or signal2 or signal3)
begin
.
End
assign internet variable = combinational good judgment;
endmodule
VHDL Interview Questions
Question 12. Difference Between Verilog And Vhdl?
Answer :
Compilation
VHDL. Multiple layout-units (entity/structure pairs), that are living in the identical machine file, can be one at a time compiled if so preferred. However, it is ideal layout exercise to maintain every design unit in it is own machine file wherein case separate compilation have to not be an trouble.
Verilog. The Verilog language is still rooted in it's local interpretative mode. Compilation is a way of dashing up simulation, however has not modified the unique nature of the language. As a result care have to be keen on each the compilation order of code written in a single report and the compilation order of more than one documents. Simulation outcomes can change through sincerely converting the order of compilation.
Data types
VHDL. A multitude of language or user described information kinds may be used. This may suggest committed conversion features are needed to convert items from one kind to some other. The choice of which records types to use need to be considered wisely, particularly enumerated (summary) records types. This will make models less complicated to write, clearer to read and avoid unnecessary conversion functions which can clutter the code. VHDL can be desired as it permits a multitude of language or user defined statistics sorts for use.
Verilog. Compared to VHDL, Verilog statistics sorts a re very simple, clean to apply and very a good deal geared in the direction of modeling hardware structure in place of abstract hardware modeling. Unlike VHDL, all records types used in a Verilog model are defined by way of the Verilog language and no longer by using the person. There are net data kinds, for instance wire, and a register data type known as reg. A model with a sign whose type is one of the net facts types has a corresponding electrical twine within the implied modeled circuit. Objects, this is alerts, of kind reg preserve their price over simulation delta cycles and should not be stressed with the modeling of a hardware sign up. Verilog can be desired due to it's simplicity.
Design reusability
VHDL. Procedures and capabilities can be placed in a package deal in order that they're avail capable of any layout-unit that desires to apply them.
Verilog. There isn't any idea of programs in Verilog. Functions and approaches used within a version need to be described within the module. To make capabilities and tactics normally accessible from specific module statements the features and approaches have to be located in a separate machine report and protected the usage of the `consist of compiler directive.
Perl Scripting Interview Questions
Question thirteen. Can You Tell Me Some Of System Tasks And Their Purpose?
Answer :
$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.
The most beneficial of those is $display.This can be used for showing strings, expression or values of variables.
Here are a few examples of utilization.
$show("Hello oni");
--- output: Hello oni
$show($time) // current simulation time.
--- output: 460
counter = four'b10;
$show(" The rely is %b", counter);
--- output: The count is 0010
$reset resets the simulation returned to time zero; $forestall halts the simulator and puts it in interactive mode where the person can enter instructions; $finish exits the simulator lower back to the working gadget
Question 14. Can You List Out Some Of Enhancements In Verilog 2001?
Answer :
In earlier version of Verilog ,we use 'or' to specify a couple of detail in sensitivity list . In Verilog 2001, we can use comma as shown in the instance below.
// Verilog 2k instance for usage of comma
usually @ (i1,i2,i3,i4)
Verilog 2001 lets in us to use megastar in sensitive list in place of list all of the variables in RHS of blend logics . This removes typo mistakes and accordingly avoids simulation and synthesis mismatches, Verilog 2001 lets in port route and statistics kind in the port listing of modules as proven in the instance under
module memory (
input r,
input wr,
enter [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);
Question 15. Write A Verilog Code For Synchronous And Asynchronous Reset?
Answer :
Synchronous reset, synchronous method clock established so reset ought to not be found in sensitivity disk
eg: usually @ (posedge clk )
start if (reset)
. . . Stop
Asynchronous way clock unbiased so reset ought to be found in sensitivity list.
Eg: Always @(posedge clock or posedge reset)
begin
if (reset)
. . . End
VLSI Interview Questions
Question sixteen. What Is Pli?Why Is It Used?
Answer :
Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog packages with programs written in C language. It also presents mechanism to get right of entry to inner databases of the simulator from the C program.
PLI is used for implementing gadget calls which would were difficult to do in any other case (or impossible) the usage of Verilog syntax. Or, in other words, you can take gain of each the paradigms - parallel and hardware associated features of Verilog and sequential glide of C - the use of PLI.
Question 17. There Is A Triangle And On It There Are three Ants One On Each Corner And Are Free To Move Along Sides Of Triangle What Is Probability That They Will Collide?
Answer :
Ants can pass best along edges of triangle in either of path, allow’s say one is represented through 1 and another through zero, due to the fact there are three aspects eight combinations are feasible, while all ants are getting into identical route they won’t collide this is 111 or 000 so opportunity of now not collision is 2/eight=1/four or collision opportunity is 6/eight=three/4
Ethernet Interview Questions
Question 18. How To Write Fsm Is Verilog?
Answer :
there r particularly four approaches 2 write fsm code
the usage of 1 manner in which all input decoder, present nation, and output decoder r combine in a single procedure.
The usage of 2 manner wherein all comb ckt and sequential ckt separated in extraordinary technique
the usage of 2 process wherein enter decoder and persent nation r integrate and output decoder seperated in other technique
using three technique where all 3, input decoder, gift state and output decoder r separated in 3 manner.
Shell Scripting Interview Questions
Question 19. What Is Difference Between Freeze Deposit And Force?
Answer :
$deposit(variable, price);
This system project sets a Verilog register or net to the required value. Variable is the sign up or internet to be modified; value is the new value for the register or net. The price remains till there is a next driver transaction or another $deposit challenge for the identical sign up or net. This device undertaking operates identically to the ModelSim force -deposit command.
The force command has -freeze, -pressure, and -deposit alternatives. When none of those is unique, then -freeze is thought for unresolved indicators and -pressure is thought for resolved indicators. This is designed to provide compatibility with force files. But in case you pick -freeze as the default for both resolved and unresolved indicators.
Question 20. Will Case Infer Priority Register If Yes How Give An Example?
Answer :
yes case can infer precedence check in depending on coding fashion
reg r;
// Priority encoded mux,
continually @ (a or b or c or select2)
start
r = c;
case (select2)
2'b00: r = a;
2'b01: r = b;
endcase
quit
Advanced C++ Interview Questions
Question 21. Given The Following Verilog Code, What Value Of "a" Is Displayed?
Answer :
continually @(clk) start
a = 0;
a <= 1;
$show(a);
end
This is a complex one! Verilog scheduling semantics essentially imply a 4-stage deep queue for the current simulation time:
Active Events (blocking off statements)
Inactive Events (#zero delays, and so forth)
Non-Blocking Assign Updates (non-blocking off statements)
Monitor Events ($display, $screen, etc).
Since the "a = zero" is an active event, it's far scheduled into the 1st "queue".
The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.
Finally, the display statement is placed into the 4th queue. Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1.
Question 22. What Is The Difference Between The Following Two Lines Of Verilog Code?
Answer :
#5 a = b;
a = #5 b;
#5 a = b;
Wait five time units before doing the action for "a = b;".
A = #5 b; The value of b is calculated and stored in an internal temp register,After five time units, assign this stored value to a.
Question 23. What Does `timescale 1 Ns/ 1 Ps Signify In A Verilog Code?
Answer :
'timescale directive is a compiler directive.It is used to measure simulation time or delay time. Usage :`timescale / reference_time_unit : Specifies the unit of measurement for times and delays. Time_precision: specifies the precision to which the delays are rounded off.
Basic C Interview Questions
Question 24. What Is The Difference Between === And == ?
Answer :
output of "==" can be 1, 0 or X.
Output of "===" can only be 0 or 1.
When you are comparing 2 nos using "==" and if one/both the numbers have one or more bits as "x" then the output would be "X" . But if use "===" outpout would be 0 or 1.
E.G A = 3'b1x0
B = 3'b10x
A == B will give X as output.
A === B will give 0 as output.
"==" is used for comparison of only 1's and 0's .It can't compare Xs. If any bit of the input is X output will be X
"===" is used for comparison of X also.
System Administration Interview Questions
Question 25. How To Generate Sine Wav Using Verilog Coding Style?
Answer :
The easiest and efficient way to generate sine wave is using CORDIC Algorithm.
Question 26. What Is The Difference Between Wire And Reg?
Answer :
(wire,tri)Physical connection between structural elements. Value assigned by a continuous assignment or a gate output. Register type: (reg, integer, time, real, real time) represents abstract data storage element. Assigned values only within an always statement or an initial statement. The main difference between wire and reg is wire cannot hold (store) the value when there no connection between a and b like a->b, if there may be no connection in a and b, twine loose value. But reg can hold the fee even though there in no connection. Default values:twine is Z,reg is x.
ASIC Interview Questions
Question 27. How Do You Implement The Bi-directional Ports In Verilog Hdl?
Answer :
module bidirec (oe, clk, inp, outp, bidir);
// Port Declaration
enter oe;
input clk;
enter [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? A : 8'bZ ;
assign outp = b;
// Always Construct
continually @ (posedge clk)
start
b <= bidir;
a <= inp;
end
endmodule
System Verilog Interview Questions
Question 28. What Is Verilog Case (1) ?
Answer :
wire [3:0] x;
always @(...) start
case (1'b1)
x[0]: SOMETHING1;
x[1]: SOMETHING2;
x[2]: SOMETHING3;
x[3]: SOMETHING4;
endcase
stop
The case assertion walks down the listing of cases and executes the first one which fits. So right here, if the bottom 1-bit of x is bit 2, then something3 is the statement so that it will get done (or selected by the logic).
Question 29. Why Is It That "if (2'b01 & 2'b10)..." Doesn't Run The True Case?
Answer :
This is a famous coding blunders. You used the bit sensible AND operator (&) in which you supposed to apply the logical AND operator (&&).
Universal Verification Methodology (UVM) Interview Questions
Question 30. What Are Different Types Of Verilog Simulators ?
Answer :
There are specially two types of simulators available.
Event Driven
Cycle Based
Event-based Simulator:
This Digital Logic Simulation technique sacrifices performance for rich capability: every active sign is calculated for every tool it propagates thru for the duration of a clock cycle. Full Event-based totally simulators aid four-28 states; simulation of Behavioral HDL, RTL HDL, gate, and transistor representations; complete timing calculations for all gadgets; and the overall HDL general. Event-primarily based simulators are like a Swiss Army knife with many different functions but none are especially speedy.
Cycle Based Simulator:
This is a Digital Logic Simulation approach that gets rid of pointless calculations to gain huge overall performance gains in verifying Boolean good judgment:
Results are best tested at the quit of every clock cycle; and
The digital common sense is the simplest a part of the layout simulated (no timing calculations). By proscribing the calculations, Cycle primarily based Simulators can provide big increases in performance over conventional Event-based totally simulators.
Cycle primarily based simulators are more like a high speed electric powered carving knife in contrast because they recognition on a subset of the most important problem: common sense verification.
Cycle based totally simulators are nearly continuously used in conjunction with Static Timing verifier to atone for the lost timing statistics coverage.
