Top 100+ Universal Verification Methodology (uvm) Interview Questions And Answers
Question 1. What Is Uvm? What Is The Advantage Of Uvm?
Answer :
UVM (Universal Verification Methodology) is a normalized technique for checking the both complex and straightforward advanced structure in basic manner.
UVM Features:
First philosophy and second assortment of class libraries for Automation
Reusability through test seat
Attachment and Play of confirmation IPs
Conventional Test seat Development
Seller and Simulator Independent
Shrewd Test seat for example produce lawful improvement as from pre-arranged inclusion plan
Backing CDV – Coverage Driven Verification
Backing CRV – Constraint Random Verification
UVM normalized under the Accelerate System Initiative
Register displaying
Question 2. Uvm Derived From Which Language?
Answer :
Here is the definite association between SV, UVM, OVM and different techniques.
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Question 3. What Is The Difference Between Uvm_component And Uvm_object? Or on the other hand We Already Have Uvm_object, Why Do We Need Uvm_component Which Is Actually Derived Class Of Uvm_object?
Answer :
uvm_component:
Semi Static Entity (after form stage it is accessible all through the reenactment).
Continuously attached to a given equipment (DUT Interface) or a TLM port.
Having staging instrument for control the conduct of reproduction.
Design Component Topology.
uvm_object:
Dynamic Entity (makes when required, move from one part to other and then dereference).
Not attached to a given equipment or any TLM port.
Not staging system.
Question 4. Which Uvm Phase Is Top - Down, Bottom – Up and Parallel?
Answer :
Just form stage is a top-down and different stages are base up aside from run stage which is equal. The fabricate stage works top-down since the test seat chain of importance might be arrange so we have to manufacture the branches before leafs.
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Question 5. Why Build Phase Is Top – Down and Connect Phase Is Bottom – Up?
Answer :
The associate stage is planned to be utilized for making TLM associations between segments, which is the reason it happen after form stage. It stir base up so its got the right execution as far as possible up the plan order, whenever worked top-down this would be unrealistic.
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Question 6. Which Phase Is Function and Which Phase Is Task?
Answer :
Just run stage is an errand (tedious stage) and different stages are capacities (non-blocking).
Question 7. Which Phase Takes More Time And Why?
Answer :
As recently said the run stage is executed as assignment and staying all are work. run stage will get executed from beginning of reproduction to work the finish of reenactment. run stage is tedious, where the experiment is running.
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Question 8. How Uvm Phases Initiate?
Answer :
UVM stages start by calling run test ("test1") in top module. At the point when run test() strategy call, it initially make the object of test top and then call all stages.
Question 9. How Test Cases Run From Simulation Command Line?
Answer :
In top module compose run test(); for example Try not to give anything in contention.
At that point in order line: +UVM_TESTNAME=test name.
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Question 10. Distinction Between Module and Class Based Tb?
Answer :
A module is a static article present continually during of the reproduction.
A Class is a powerful item since they can go back and forth during the existence time of reenactment.
Question 11. What Is Uvm_config_db? What Is Difference Between Uvm_config_db and Uvm_resource_db?
Answer :
Uvm_config_db is a parameterized class utilized for design of various kind of parameter into the uvm database, So that it tends to be utilized by any segment in the lower level of pecking order.
Uvm_config_db is an accommodation layer based on uvm_resource_db, yet that comfort is significant. Specifically, uvm_resource_db utilizes a "last compose wins" approach. The uvm_config_db, then again, takes a gander at where things are in the pecking order up through end_of_elaboration, so "parent wins." Once you start start_of_simulation, the config_db turns out to be "last compose wins."
The entirety of the capacities in uvm_config_db#(T) are static, so they should be considered utilizing the :: administrator. It is reached out from the uvm_resource_db#(T), so it is kid class of uvm_resource_db#(T).
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Question 12. What Is The Advantage And Difference Of 'uvm_component_utils() And 'uvm_object_utils()?
Answer :
The utile macros characterize the framework expected to empower the item/part for right production line activity.
The explanation there are two macros is on the grounds that the manufacturing plant configuration design fixes the quantity of contentions that a constructor can have. Classes got from uvm_object have constructors with one contention, a string name. Classes got from uvm_component have two contentions, a name and an uvm_component parent.
The two 'uvm_*utile macros embeds code that gives you a processing plant make() technique that agents calls to the constructors of uvm_object or uvm_component. You have to utilize the separate full scale with the goal that the right constructor contentions get went through. This implies you can't include additional constructor contentions when you stretch out these classes so as to have the option to utilize the UVM processing plant.
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Question 13. Distinction Between 'uvm_do And 'uvm_rand_send ?
Answer :
uvm_do play out the beneath steps:
Make
Start thing
Randomize
Finish thing
get reaction (discretionary)
While 'uvm_rand_send play out all the above strides with the exception of make. Client needs to make arrangement/succession thing.
Question 14. Contrast Between Uvm_transaction And Uvm_seq_item?
Answer :
class uvm_sequence_item expands uvm_transaction
Uvm_sequence_item stretched out from uvm_transaction just, uvm_sequence_item class has greater usefulness to help succession and sequencer highlights. Uvm_sequence_item gives the snares to sequencer and arrangement, So you can create exchange by utilizing succession and sequencer , and uvm_transaction give just essential strategies like do print and do record and so on .
Question 15. Is Uvm Is Independent Of Systemverilog?
Answer :
UVM is a philosophy dependent on Systemverilog language and isn't a language all alone. It is a normalized system that characterizes a few prescribed procedures in confirmation to empower proficiency as far as reuse and is additionally right now part of IEEE 1800.2 working gathering.
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Question 16. What Are The Benefits Of Using Uvm?
Answer :
A portion of the advantages of utilizing UVM are:
Measured quality and Reusability – The philosophy is planned as particular segments (Driver, Sequencer, Agents , env and so on) which empowers reusing segments across unit level to multi-unit or chip level check just as across ventures.
Isolating Tests from Test seats – Tests regarding boost/sequencers are kept separate from the genuine test seat chain of importance and subsequently there can be reuse of improvement across various units or across ventures.
Test system free – The base class library and the technique is upheld by all test systems and subsequently there is no reliance on a particular test system.
Better control on Stimulus age – Sequence approach gives great control on boost age. There are a few manners by which successions can be created which incorporates randomization, layered arrangements, virtual groupings and so on which gives a decent control and rich upgrade age ability.
Simple setup – Config components disentangle design of articles with profound chain of importance. The arrangement system helps in effectively designing diverse test seat segments dependent on which check condition utilizes it and without agonizing over how profound any segment is in test seat pecking order.
Industrial facility system – Factory instruments disentangles alteration of parts without any problem. Making every part utilizing processing plant empowers them to be superseded in various tests or conditions without changing basic code base.
Question 17. Would we be able to Have User Defined Phase In Uvm?
Answer :
Notwithstanding the predefined stages accessible in uvm , the client has the choice to add his own stage to a part. This is ordinarily done by broadening the uvm_phase class the constructor needs to call super. new which has three contentions.
Name of the stage assignment or capacity
Top down or base up stage
Errand or capacity
The call task or call_func and get_type_name should be actualized to finish the expansion of new stage.
The following is a basic model
Model:
Class custom stage broadens uvm_phase;
Capacity new ();
Super. New ("custom", 1, 1);
End work
Errand call task (uvm_component parent);
My_comp_type comp;
On the off chance that ( $cast(comp, parent) )
comp.custom stage ();
End task
Virtual capacity string get_type_name ();
Return "custom";
End work
End class
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Question 18. What Is Uvm Ral Model? Why It Is Required?
Answer :
In a confirmation setting, a register model (or register reflection layer) is a lot of classes that model the memory mapped conduct of registers and recollections in the DUST so as to encourage improvement age and practical checking (and alternatively a few parts of useful inclusion). The UVM gives a lot of base classes that can be stretched out to actualize far reaching register demonstrating capacities.
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Question 19. What Is The Difference Between New() And Create?
Answer :
We as a whole think about new () technique that is use to distribute memory to an article occasion. In UVM (and OVM), the make () strategy causes an item case to be made from the plant. This permits you to utilize processing plant abrogates to supplant the ideal article with an object of an alternate kind without recoding.
Question 20. What Is Analysis Port?
Answer :
Examination port (class uvm_tlm_analysis_port) — a particular sort of exchange level port that can be associated with zero, one, or numerous investigation sends out and through which a segment may call the strategy compose actualized in another segment, explicitly an endorser.
port, fare, and devil classes utilized for exchange examination.
uvm_analysis_port
Communicates an incentive to all supporters actualizing an uvm_analysis_imp.
uvm_analysis_imp
Gets all exchanges communicated by an uvm_analysis_port.
uvm_analysis_export
Fares a lower-level uvm_analysis_imp to its parent.
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Question 21. What Is Tlm Fifo?
Answer :
In more straightforward words TLM FIFO is a FIFO between two UVM segments, ideally among Monitor and Scoreboard. Screen continue sending the DATA, which will be put away in TLM FIFO, and Scoreboard can get information from TLM FIFO at whatever point required.
/make a FIFO with profundity 4
tlm_fifo = new ("uvm tlm_fifo", this, 4);
Question 22. How Sequence Starts?
Answer :
Start thing begins the succession
Virtual undertaking start thing (uvm_sequence_item thing,
int set need = - 1,
Uvm_sequencer_base sequencer = invalid )
Start thing and finish thing together will start activity of a succession thing. In the event that the thing has not as of now been instated utilizing make thing, at that point it will be introduced here to utilize the default sequencer indicated by m_sequencer.
Question 23. What Is The Difference Between Uvm Ral Model Backdoor Write/perused And Front Door Write/read?
Answer :
Text style entryway get to implies utilizing the standard access component outer to the DUTY to peruse or keep in touch with a register. This normally includes arrangements of tedious exchanges on a transport interface.
Indirect access get to implies getting to a register straightforwardly by means of progressive reference or outside the language through the PLI. An indirect access reference for the most part in 0 reenactment time.
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Question 24. What Is Objection?
Answer :
The complaint system in UVM is to permit various leveled status correspondence among segments which is useful in choosing the finish of test.
There is a worked in complaint for each in-constructed stage, which gives an approach to parts and items to synchronize their testing action and show when it is protected to end the stage and, at last, the test end.
The segment or arrangement will bring up a stage criticism toward the start of a movement that must be finished before the stage stops, so the protest will be dropped toward the finish of that action. When the entirety of the brought up criticisms are dropped, the stage ends.
Bringing up a criticism: phase.raise_objection (this);
Dropping a protest: phase.drop_objection (this);
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Question 25. What Is M_sequencer? Or on the other hand Difference Between M_sequencer And M_sequencer?
Answer :
M_sequencer is the default handle for uvm_vitual_sequencer and m_sequencer is the attach for kid sequencer.
M_sequencer is the conventional uvm_sequencer pointer. It will consistently exist for the uvm_sequencer and is introduced when the grouping is begun.
P_sequencer is a composed explicit sequencer pointer, made by enlisting the arrangement to the sequencer utilizing macros ('uvm_declare_p_sequencer) . Being type explicit, you will have the option to get to anything added to the sequencer (for example pointers to different sequencers, and so on.). M_sequencer won't exist in the event that we have not enrolled the arrangement with the 'uvm_declare_p_sequencer macros.
The disadvantage of m_sequencer is that once the m_sequencer is characterized, one can't run the succession on some other sequencer type.
Question 26. What Is The Difference Between Active Mode And Passive Mode With Respect To Agent?
Answer :
A specialist is an assortment of a sequencer, a driver and a screen.
In dynamic mode, the sequencer and the driver are built and improvement is produced by groupings sending arrangement things to the driver through the sequencer. Simultaneously the screen gathers pin level movement into investigation exchanges.
In detached mode, just the screen is built and it plays out a similar capacity as in a functioning specialist. Accordingly, your inactive specialist has no requirement for a sequencer. You can set up the screen utilizing a design object.
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Question 27. What Is The Difference Between Copy And Clone?
Answer :
The inherent duplicate () strategy executes the __m_uvm_field_automation() technique with the necessary duplicate code as characterized by the field macros (whenever utilized) and afterward calls the implicit do duplicate() virtual capacity. The implicit do duplicate () virtual capacity, as characterized in the uvm_object base class, is likewise a vacant technique, so if field macros are utilized to characterize the fields of the exchange, the inherent duplicate() strategy will be populated with the correct code to duplicate the exchange fields from the field full scale definitions and afterward it will execute the void do duplicate() technique, which will play out no extra action.
The duplicate() technique can be utilized varying in the UVM test seat. One regular spot where the duplicate() technique is utilized is to duplicate the tested exchange and pass it into a sb_calc_exp() (scoreboard compute expected) outside capacity that is every now and again utilized by the scoreboard indicator.
The clone () strategy calls the make () technique (builds an object of a similar sort) and afterward calls the duplicate() technique. It is a one-advance order to make and duplicate a current item to another article handle.
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Question 28. What Is Uvm Factory?
Answer :
UCM Factory is utilized to fabricate (make) UVM items and parts. Aside from making the UVM items and parts the processing plant idea basically implies that you can alter or substitute the idea of the segments made by the production line without making changes to the test seat.
For instance, on the off chance that you have composed two driver classes, and nature utilizes just one of them. By enrolling both the drivers with the processing plant, you can request that the production line substitute the current driver in condition with the other sort. The code expected to accomplish this is insignificant, and can be written in the test.
Question 29. What Are The Types Of Sequencer? Clarify Each?
Answer :
There are two sorts of sequencers:
uvm_sequencer #(REQ, RSP) :
At the point when the driver starts new demands for groupings, the sequencer chooses a succession from a rundown of accessible arrangements to create and convey the following thing to execute. So as to do this, this sort of sequencer is typically associated with a driver uvm_driver #(REQ, RSP).
uvm_push_sequencer #(REQ, RSP) :
The sequencer pushes new succession things to the driver, however the driver can hinder the thing stream when it's not prepared to acknowledge any new exchanges. This kind of sequencer is associated with a driver of type uvm_push_driver # (REQ, RSP).
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