Top 100+ System Verilog Interview Questions And Answers
Question 1. What Is Callback ?
Answer :
In pc programming, a callback is executable code that is exceeded as a controversy to different code. It allows a lower-level software program layer to call a subroutine (or feature) described in a higher-stage layer.
Question 2. What Is Factory Pattern ?
Answer :
Factory Pattern Concept :
Methodologies like OVM and VMM make heavy use of the factory concept. The factory method sample is an item-orientated layout pattern. Like other creational styles, it offers with the hassle of making objects (products) with out specifying the exact magnificence of object with a view to be created. The manufacturing facility method layout sample handles this problem via defining a separate approach for creating the gadgets, whose subclasses can then override to specify the derived kind of product so one can be created. More usually, the time period manufacturing unit approach is frequently used to refer to any technique whose main cause is advent of objects.
Or in easy terms factory pattern help in advent of the item while you dont understand the exact type of the object. The ordinary way of making the item is :
01.// Normal Type based totally item introduction
02.
03.// Class object
04.Class my_class;
05.Int i;
06.Endclass
07.
08.Program foremost;
09.// Create item type my_class
10.My_class obj1;
11.Obj1 = new
12.Endprogram
thirteen.
14.// Using Factory I must be capable of do the subsequent
15.
16.Software major;
17.Base_class my_class_object;
18.
19.Base_class = factory.Create_object("my_class"); // See right here the sort of the object to be created is handed as a string so we dont recognize the exact form of the object
20.Endprogram
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Question three. Explain The Difference Between Data Types Logic And Reg And Wire ?
Answer :
Wire are Reg are present within the verilog and device verilog provides one extra information type referred to as common sense.
Wire : Wire statistics type is used in the continuous assignments or ports list. It is dealt with as a cord So it cannot keep a price. It can be driven and study. Wires are used for connecting one of a kind modules.
Reg : Reg is a date garage element in system verilog. Its now not a real hardware check in however it could shop values. Register preserve there cost till subsequent task assertion.
Logic : System verilog brought this extra datatype extends the rand eg kind so it can be driven by a single motive force inclusive of gate or module. The primary distinction among logic dataype and reg/twine is that a good judgment may be pushed by means of each non-stop task or blocking off/non blocking off task.
Question four. What Is The Need Of Clocking Blocks ?
Answer :
It is used to specify synchronization characteristics of the design
It Offers a clean way to pressure and sample alerts
Provides race-free operation if input skew > 0
Helps in testbench riding the alerts at the proper time
Features
- Clock specification
- Input skew,output skew
- Cycle postpone (##)
Can be declared inside interface,module or program
Example :
01.Module M1(ck, enin, din, enout, dout);
02.Enter ck,enin;
03.Enter [31:0] din ;
04.Output enout ;
05.Output [31:0] dout ;
06.
07.Clocking sd @(posedge ck);
08.Input #2ns ein,din ;
09.Output #3ns enout, dout;
10.Endclocking:sd
eleven.
12.Reg [7:0] sab ;
13.Initial begin
14.Sab = sd.Din[7:0];
15.Give up
16.Endmodule:M1
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Question 5. What Are The Ways To Avoid Race Condition Between Testbench And Rtl Using Systemverilog?
Answer :
There are mainly following approaches to keep away from the race circumstance among testbench and RTL using machine verilog
Program Block
Clocking Block
Using non blocking off assignments.
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Question 6. What Are The Types Of Coverages Available In Sv ?
Answer :
Using covergroup : variables, expression, and their cross
Using cover key-word : residences
Question 7. What Is Oops?
Answer :
Here are a few great OOP links on SystemVerilog OOP which can be used as a good place to begin/reference.
Object Oriented Programming for Hardware Verification
Improve Your SystemVerilog OOP Skills with the aid of Learning Principles and Patterns
SystemVerilog OOP OVM Feature Summary
Enhancing SystemVerilog with AOP Concepts (On how to mimic AOP features in OOP, correct for guyz coming from e heritage)
Testbench.In OOP Tutorial
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Question 8. What Is The Need Of Virtual Interfaces ?
Answer :
An interface encapsulate a set of inter-related wires, together with their guidelines (through modports) and synchronization info (via clocking block). The main usage of interface is to simplify the connection among modules.
But Interface cannot be instantiated interior application block, class (or comparable non-module entity in SystemVerilog). But they needed to be pushed from verification environment like elegance. To remedy this problem digital interface concept was introduced in SV.
Virtual interface is a statistics type (that means it is able to be instantiated in a category) which preserve connection with an interface (that suggests the class can power the interface the usage of the virtual interface). It gives a mechanism for setting apart abstract models and check packages from the actual alerts that make up the design. Another large advantage of digital interface is that magnificence can dynamically connect to exclusive physical interfaces in run time.
Question nine. What Is The Difference Between Mailbox And Queue?
Answer :
A queue is a variable-length, ordered collection of homogeneous factors. A Queue is similar to 1 dimensional unpacked array that grows and shrinks automatically. Queues may be used to model a final in, first out buffer or first in, first out buffer.
// Other records type as reference
// int q[]; dynamic array
// int q[5]; fixed array
// int q[string]; partner array
// consist of <
// List#(integer) List1; //
int q[$] = 2, 4, 8 ;
int p[$];
int e, pos;
e = q[0]; // study the first (leftmost) object
e = q[$]; // study the last (rightmost) object
q[0] = e; // write the primary object
p = q; // study and write whole queue (replica)
A mailbox is a verbal exchange mechanism that permits messages to be exchanged between strategies. Data may be sent to a mailbox by using one procedure and retrieved by using another.
VHDL Interview Questions
Question 10. What Data Structure You Used To Build Scoreboard?
Answer :
In SV, we use mailbox to get facts from extraordinary modules and compare the result.
Magnificence Scoreboard;
mailbox drvr2sb;
mailbox rcvr2sb;
characteristic new(mailbox drvr2sb,mailbox rcvr2sb);
this.Drvr2sb = drvr2sb;
this.Rcvr2sb = rcvr2sb;
endfunction:new
mission start();
packet pkt_rcv,pkt_exp;
forever
start
rcvr2sb.Get(pkt_rcv);
$show(" %0d : Scorebooard : Scoreboard acquired a packet from receiver ",$time);
drvr2sb.Get(pkt_exp);
if(pkt_rcv.Examine(pkt_exp))
$show(" %0d : Scoreboardd :Packet Matched ",$time);
else
$root.Errors++;
stop
endtask : start
endclass
In VMM, we use channels to connect all of the modules and examine the result.
Class Scoreboard extends vmm_xactor;
Packet_channel drvr2sb_chan;
Packet_channel rcvr2sb_chan;
feature new(string inst = "class",
int unsigned stream_id = -1,
Packet_channel drvr2sb_chan = null,
Packet_channel rcvr2sb_chan = null);
super.New("sb",inst,stream_id);
if(drvr2sb_chan == null)
`vmm_fatal(this.Log,"drvr2sb_channel isn't always constructed");
else
this.Drvr2sb_chan = drvr2sb_chan;
if(rcvr2sb_chan == null)
`vmm_fatal(this.Log,"rcvr2sb_channel is not built");
else
this.Rcvr2sb_chan = rcvr2sb_chan;
`vmm_note(log,"Scoreboard created ");
endfunction:new
project primary();
Packet pkt_rcv,pkt_exp;
string msg;
top notch.Foremost();
forever
start
rcvr2sb_chan.Get(pkt_rcv);
$display(" %0d : Scoreboard : Scoreboard acquired a packet from receiver ",$time);
drvr2sb_chan.Get(pkt_exp);
if(pkt_rcv.Compare(pkt_exp,msg))
$show(" %0d : Scoreboard :Packet Matched ",$time);
else
`vmm_error(this.Log,$psprintf(" Packet MissMatched n %s ",msg));
stop
endtask : fundamental
endclass
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Question eleven. What Is The Difference Between $random() And $urandom()?
Answer :
$random device function returns a 32-bit signed random range every time it's miles known as
$urandom gadget feature returns a 32-bit unsigned random range whenever it's miles referred to as. (newly introduced in SV, now not found in verilog)
VLSI Interview Questions
Question 12. What Is Scope Randomization?
Answer :
Scope randomization ins SystemVerilog lets in task of unconstrained or restrained random cost to the variable inside current scope
01.Module MyModule;
02.Integer var, MIN;
03.
04.Initial begin
05.MIN = 50;
06.For ( int i = zero;i start
07.If( randomize(var) with var < 100 ; var > MIN ;)
08.$display(" Randomization sucsessfull : var = %0d Min = %0d",var,MIN);
09.Else
10.$display("Randomization failed");
eleven.End
12.
13.$end;
14.Cease
15.Endmodule
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Question thirteen. List The Predefined Randomization Methods.
Answer :
randomize
pre_randomize
post_randomize
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Question 14. What Is The Dfference Between Always_combo And Always@(*)?
Answer :
From SystemVerilog LRM three.1a:-
always_comb get completed once at time 0, usually @* waits till a alternate happens on a signal inside the inferred sensitivity listing
Statement within always_comb can't have blockading timing, occasion control, or fork-be part of statement. No such limit of usually @*
Optionally EDA tool would possibly carry out extra tests to warn if the conduct within always_comb method would not represent combinatorial logic
Variables at the left-hand side of assignments within an always_comb system, together with variables from the contents of a referred to as feature, shall now not be written to by means of another strategies, whereas usually @* permits more than one techniques to jot down to the equal variable.
Always_comb is touchy to adjustments within content material of a characteristic, while continually @* is handiest sensitive to modifications to the arguments to the feature.
A small SystemVerilog code snippet to illustrate #five
01.Module dummy;
02.Logic a, b, c, x, y;
03.
04.// Example void function
05.Feature void my_xor;
06.Enter a; // b and c are hidden input here
07.X = a ^ b ^ c;
08.Endfunction : my_xor
09.
10.Feature void my_or;
11.Enter a; // b and c are hidden input right here
12.Y = a 13.Endfunction : my_xor
14.
15.Always_comb // equal to continually(a,b,c)
sixteen.My_xor(a); // Hidden inputs are also delivered to sensitivity listing
17.
18.Continually @* // equivalent to always(a)
19.My_or(a); // b and c are not added to sensitivity list
20.Endmodule
Question 15. What Is The Use Of Packages?
Answer :
In Verilog statement of data/venture/function inside modules are particular to the module simplest. They can't be shared among modules. Agreed, we can attain the identical thru move module referencing or via together with the documents, both of which might be regarded to be no longer a fantastic answer.
The package deal assemble of SystemVerilog pursuits in fixing the above issue. It allows having global records/venture/feature announcement which may be used throughout modules. It can comprise module/class/feature/project/constraints/covergroup and plenty of greater declarations (for whole listing please refer phase 18.2 of SV LRM 3.1a)
The content within the package deal may be accessed the usage of either scope decision operator (::), or using import (with alternative of referencing unique or all content of the package deal).
01.Bundle ABC;
02.// Some typedef
03.Typedef enum RED, GREEN, YELLOW Color;
04.
05.// Some feature
06.Void characteristic do_nothing()
07....
08.Endfunction : do_nothing
09.
10.// You will have many one of a kind declarations right here
11.Endpackage : ABC
12.
Thirteen.// How to use them
14.Import ABC::Color; // Just import Color
15.Import ABC::*; // Import everything within the package deal
Semiconductor Interview Questions
Question sixteen. What Is The Use Of $forged?
Answer :
Type casting in SV may be achieved either thru static casting (', ', ') or dynamic casting via $solid challenge/characteristic. $solid is very similar to dynamic_cast of C++. It exams whether the casting is possible or not in run-time and errors-out if casting is not viable.
Question 17. How To Call The Task Which Is Defined In Parent Object Into Derived Class ?
Answer :
superb.Task_name();
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Question 18. What Is The Difference Between Rand And Randc?
Answer :
rand - Random Variable, identical price might come earlier than all the the possible value have been returned. Analogous to throwing a dice.
Randc - Random Cyclic Variable, identical price does not get lower back till all feasible fee had been again. Analogous to picking of card from a deck of card without changing. Resource extensive, use sparingly/judiciously
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Question 19. What Is $root?
Answer :
$root refers to the pinnacle degree instance in SystemVerilog
1.Package deal ABC;
2.$root.A; // pinnacle level example A
3.$root.A.B.C; // object C within instance B within pinnacle stage example A
Question 20. What Are Bi-directional Constraints?
Answer :
Constraints by using-default in SystemVerilog are bi-directional. That implies that the constraint solver would not observe the collection wherein the restrictions are detailed. All the variables are regarded concurrently. Even the procedural searching constrains like if ... Else ... And -> constrains, each if and else component are attempted to solve concurrently. For example (a==0) -> (b==1) shall be solved as all of the viable answer of (!(a==zero) where the person need to specify the order wherein the limitations solver shall resolve the constraints, the user can specify the order thru remedy before construct. I.E.
1....
2.Constraint XYZ
three.A interior [0:100]4.B < 20;
5.A + b > 30;
6.Resolve a earlier than b;
7.
The solution of the constraint doesn't alternate with remedy earlier than construct. But the possibility of selecting a selected solution alternate through it.
Question 22. Without Using Randomize Method Or Rand,generate An Array Of Unique Values?
Answer :
1....
2.Int UniqVal[10];
three.Foreach(UniqVal[i]) UniqVal[i] = i;
4.UniqVal.Shuffle();
five....
Question 23. Explain About Pass By Ref And Pass By Value?
Answer :
Pass by using value is the default technique through which arguments are handed into functions and tasks. Each subroutine retains a neighborhood replica of the argument. If the arguments are modified within the subroutine announcement, the adjustments do not affect the caller.
In bypass with the aid of reference functions and obligations at once get entry to the required variables exceeded as arguments.Its like passing pointer of the variable.
Instance:
challenge bypass(int i) // mission skip(var int i) bypass by reference
delay(10);
i = 1;
printf(" i is changed to %d at %dn",i,get_time(LO) );
postpone(10);
i = 2;
printf(" i is modified to %d at %dn",i,get_time(LO) );
Universal Verification Methodology (UVM) Interview Questions
Question 24. What Is The Difference Between Byte And Bit [7:0]?
Answer :
byte is signed while bit [7:0] is unsigned.
C Interview Questions
Question 25. What Is The Difference Between Program Block And Module ?
Answer :
Program block is newly delivered in SystemVerilog. It serves these purposes
It separates testbench from DUT
It facilitates in ensuring that testbench doesn't have any race condition with DUT
It affords an entry point for execution of testbench
It affords syntactic context (through software ... Endprogram) that specifies scheduling in the Reactive Region.
Having stated this the foremost distinction between module and application blocks are
Program blocks can not have usually block inner them, modules could have.
Program blocks can not incorporate UDP, modules, or different instance of application block inner them. Modules don't have one of these restrictions.
Inside a program block, program variable can most effective be assigned the use of blocking off challenge and non-program variables can handiest be assigned the use of non-blocking assignments. No such restrictions on module
Program blocks get accomplished within the re-energetic area of scheduling queue, module blocks get completed in the active vicinity
A application can call a assignment or function in modules or other packages. But a module can not name a mission or feature in a software.
Question 26. What Is The Use Of Modports ?
Answer :
Modports are part of Interface. Modports are used for specifing the direction of the signals with admire to various modules the interface connects to.
...
Interface my_intf;
twine x, y, z;
modport grasp (input x, y, output z);
modport slave (output x, y, enter z);
VLSI Design Interview Questions
Question 27. Write A Clock Generator Without Using Always Block.
Answer :
Use of for all time begin cease. If it is a complicated constantly block statement like constantly (@ posedge clk or negedge reset_)
always @(posedge clk or negedge reset_) begin
if(!Reset_) begin
facts <= 'zero;
quit else begin
information <= data_next;
give up
give up
// Using forever : slightly complex but achievable
for all time start
fork
begin : reset_logic
@ (negedge reset_);
statistics <= '0;
quit : reset_logic
start : clk_logic
@ (posedge clk);
if(!Reset_) statistics <= 'zero;
else data <= data_next;
end : clk_logic
join_any
disable fork
end
VHDL Interview Questions
Question 28. What Is Circular Dependency And How To Avoid This Problem ?
Answer :
Over specifying the solving order might result in circular dependency, for which there is no solution, and the constraint solver might give error/warning or no constraining. Example
1....
2.Int x, y, z;
3.Constraint XYZ
4.Solve x before y;
5.Solve y before z;
6.Solve z before x;
7.....
8.
Question 29. What Is Cross Coverage ?
Answer :
Queue has a certain order. It's hard to insert the data within the queue. But Linkedlist can easily insert the data in any location.
Question 30. How To Randomize Dynamic Arrays Of Objects?
Answer :
class ABC;
// Dynamic array
rand bit [7:0] data [];
// Constraints
constraint cc
// Constraining size
data.Size inside [1:10];
// Constraining individual entry
data[0] > 5;
// All elements
foreach(records[i])
if(i > zero)
facts[i] > facts
endclass : ABC
Question 31. What Is The Need Of Alias In Sv?
Answer :
The Verilog has one-way assign statement is a unidirectional venture and can comprise postpone and energy alternate. To have bidirectional brief-circuit connection SystemVerilog has delivered alias assertion.
Question 32. What Is "this"?
Answer :
"this" pointer refers to contemporary example.
Question 33. What Is Tagged Union ?
Answer :
An union is used to saved a couple of one-of-a-kind type/length of facts in the same storage vicinity.
1.Typedef union
2.Bit [31:0] a;
three.Int b;
4. Data_u;
Now here XYZ union can comprise either bit [31:0] facts or an int facts. It may be written with a piece [31:0] information and study-lower back with a int facts. There is not any type-checking executed.
In the case in which we need to implement that the study-lower back facts-kind is equal as the written facts-type we are able to use tagged union which is declared the usage of the qualifier tagged. Whenever an union is defined as tagged, it shops the tag records at the side of the value (in rate of few more bits). The tag and values can best be up to date together the usage of a statically kind-checked tagged union expression. The facts member value can be examine with a type that is regular with modern tag value, making it impossible to write down one kind and examine any other form of value in tagged union. (the info of which can be determined in phase three.10 and seven.15 of SV LRM three.1a).
01.Typedef union tagged
02.Bit [31:0] a;
03.Int b;
04. Data_tagged_u;
05.
06.// Tagged union expression
07.Data_tagged_u data1 = tagged a 32'h0;
08.Data_tagged_u data2 = tagged b 5;
09.
10.// Reading lower back the value
11.Int xyz = data2.B;
VLSI Interview Questions
Question 34. What Is "scope Resolution Operator"?
Answer :
extern keyword lets in out-of-frame method assertion in classes. Scope decision operator ( :: ) links technique announcement to magnificence announcement.
Magnificence XYZ;
// SayHello() can be declared out of doors the body
// of the class
extern void assignment SayHello();
endclass : XYZ
void mission XYZ :: SayHello();
$Message("Hello !!!N");
endtask : SayHello
Question 35. What Is The Difference Between Bits And Logic?
Answer :
bits is two-valued (1/zero) and good judgment is 4-valued (zero/1/x/z)
Question 36. What Is The Difference Between $rose And Posedge?
Answer :
posedge go back an event, while $rose returns a Boolean fee. Therefore they may be no longer interchangeable.
Semiconductor Interview Questions
Question 37. What Is Layered Architecture ?
Answer :
In SystemVerilog primarily based restrained random verification environment, the test surroundings is split into a couple of layered as shown within the parent. It permits verification issue re-use throughout verification projects.
Question 38. What Is The Difference Between Initial Block And Final Block?
Answer :
There are many difference among preliminary and final block. I am listing the few differences this is coming to thoughts now.
The most apparent one : Initial blocks get carried out at the start of the simulation, final block on the cease of simulation
Final block has to be achieved in zero time, which means it can't have any put off, wait, or non-blockading assignments. Initial block doesn't have any such restrictions of execution in zero time (and can have put off, wait and non-blocking off statements)
Final block may be used to show statistical/genaral data regarding the fame of the execution like this:-
1.Very last begin
2.$display("Simulation Passed");
3.$show("Final price of xyz = %h",xyz);
four.$show("Bye :: So long, and Thanks for all of the fishes");
five.Quit
Question 39. How To Check Weather A Handles Is Holding Object Or Not ?
Answer :
It is essentially checking if the item is initialized or not. In SystemVerilog all uninitialized object handles have a special value of null, and consequently whether it's far keeping an item or no longer can be determined out with the aid of evaluating the object deal with to null. So the code will seem like:-
01.Usb_packet My_usb_packet;
02....
03.If(My_usb_packet == null) start
04.// This loop gets exited if the take care of isn't maintaining any object
05.....
06.Quit else begin
07.// Hurray ... The cope with is conserving an object
08....
09.Quit
