Interview Questions.

Question 1. How A Latch Gets Inferred In Rtl Design?

Answer :

A latch gets inferred in the RTL design:-

When there's no “else / default” statement in the “if / case” statements; in brief if all possibilities of the conditions aren't included.
When all the outputs reg are not assigned the values in every condition of the “if / case” announcement and a few are ignored, on the overlooked indicators a latch gets inferred.
Question 2. Does A Latch Get Inferred When There Is No Else Statement But Multiple Ifs Covering Whole Functionality?

Answer :

Conceptually no latch must be inferred however now and again the synthesis equipment are not wise enough and they could infer a latch. In order to keep away from that, the most secure way is to apply an “else / default” assertion in “if / case” respectively.

Verilog Interview Questions
Question 3. If There Is An Asynchronous Feedback Loop What Is The Problem?

Answer :

If there's an asynchronous loop in the layout the circuit turns into oscillatory or it may attain a strong kingdom in which it might get hung and it could not get out.

Question four. If An Oscillatory Circuit Is There; What Happens During (a) Rtl Synthesis (b) Simulation?

Answer :

During the RTL synthesis, the synthesis tool will supply a warning during synthesis about the combinatorial feedback loop.
During the simulation the simulation gets stopped saying the Iteration limit reached.
Analog Communication Tutorial
Question five. Where Can We Use Linting Tools ? Can We Use Them To Debug Syntax?

Answer :

Linting equipment are used to evaluate the design for the synthesizability of the layout. These tools are use to test for ability mismatches among simulation and synthesis. No they're now not used to test the syntax.

VHDL Interview Questions
Question 6. What Can Be Done To Break The Combinational Loop?

Answer :

By adding synchronous factors inside the route. If it's far actually wished and if the layout allows then with the aid of including the buffers inside the route.

Question 7. Why We Use B.A (blockading Assignments) And N.B.A (non Blocking Assignments)?

Answer :

B.A are used to model combinatorial logic because the value is of non-stop mission and doesn’t depend on the preceding value, even as N.B.A are used to version sequential circuits because the preceding cost is needed to propagate.

VLSI Interview Questions
Question 8. What Will Be The Output Of The Following Code?
Always ( * )
Begin
A = B + D;
A = C + B;
End

Answer :

This is truely a race condition and the device will take the remaining undertaking on “a”.

Question nine. Is There A Latch In The Following Code? What If The “sel” Value Is “x”. What Will Be The Simulation Result?
Always @ ( En )
Begin
Dout = 0
Case ( Sel )
0: Dout = In ;
End

Answer :

No There is no Latch as dout=zero before the case declaration will be carried out. Even if the “sel” price is “X”, no latch might be fashioned as “dout” has been already initialized to “0”.

Analog Communication Interview Questions
Question 10. Is There A Latch In The Following Code? What If The “sel” Value Is “x”. What Will Be The Simulation Result?
Always @ ( En )
Begin
Dout = zero
Case ( Sel )
0: Dout = In ;
Default : Dout = 1;
End

Answer :

No There is no latch because the default declaration is gift and the output might be govern through the case announcement.

Question 11. If No Parameters In The Always Sensitivity List, How The Always Block Executes?

Answer :

It will repeat itself like a for all time loop but the performance will degrade.

Application Security Interview Questions
Question 12. Tell The Scenarios Where Synthesis Error Occurs.?

Answer :

A synthesis error can arise inside the following scenarios:

When there may be a couple of assignments on the identical sign in two distinctive blocks, “a multiple driver observed” message will come.
When there is combination of asynchronous reset with a few other signal and that signal isn't used within the sensitivity listing; basically blending of multiple edges and synchronous and asynchronous elements aren't allowed.
No detail inside the constantly block sensitivity list.
Mixing of B.A and N.B.A on the identical sign in two distinct conditional statements.
If reg datatypes are utilized in assign statements, and many others.
Verilog Interview Questions
Question thirteen. Is The Following Code Synthesizable?
Always @ (posedge Clk1 Or Negedge Clk2
) Begin
If (!Clk2)
Dout <= 0;
Else
Dout<= Din;
End

Answer :

Yes it's miles synthesizable attempt to read clk2 as active low reset.

Question 14. Are The Following Codes Are Synthesizable ? Is There Any Difference In The Synthesis Result Of (i) And (ii)?<
(i) Always @ (posedge Clk1 Or Negedge Clk2)
Begin
If (!Clk2 && A)
Dout <= 0;
Else
Dout<= Din;
End
(ii)

continually @ (posedge Clk1 Or Negedge Rst)
Begin
If (!Rst && A)
Dout <= 0;
Else
Dout<= Din;
End

Answer :

Both aren't synthesizable as there may be a blending of asynchronous and synchronous detail within the if situation.