Interview Questions.

Top 100+ Physical Design Engineer Interview Questions And Answers

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Top 100+ Physical Design Engineer Interview Questions And Answers

Question 1. Why Metal Density Rules Are Important?

Answer :

Metal Density policies cope with metallic over-etching and metal raise off issues encountered durinf manufacturing process.

Question 2. Why Power Stripes Routed In The Top Metal Layers?

Answer :

Power routes typically behavior a whole lot of modern. In order to reduce effect of IR drop, we need to make these routes much less resistive. Top steel layers are thicker and offer lesser resistance. This enables to reduce IR drop.

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Question 3. Types Of Checks That Can Be Done In Prime Time ?

Answer :

Timing (setup, hold, transition), layout constraints, nets, noise, clock skew and evaluation insurance.

Question 4. How Do You Validate Your Floorplan And What Analysis You Do During Floorplan?

Answer :

Overlapping of macros.
Global direction congestion -> in an effort to finalize Min. Channel spacing.
Allowable IR drop.
Physical data of the design (report_design_physical)
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Question 5. How Many Clocks You Had In Your Designs? How Did You Do Cts For The Same?

Answer :

I had five clocks in my designs, sys_clk, sys_rclk, uart_clk, g_clk and scan_clk, wherein sys_clk, g_clk and uart_clk logically one of a kind to scan_clk.

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Question 6. Did You Get Antenna Problem In Your Project For All The Metal Layers? How Did You Fix Them?

Answer :

Metal Jumper and Antenna diode are two methods to solve Antenna violations. But Metal Jumper is favored method because it does no longer want exchange to the Netlist and site. This methodology works for antenna violations on all metallic layers except for the pinnacle most layer. In this methodology, we are able to transfer the small part of routing to higher degree metal near the region of failing gate. This will make certain that gathered prices on metal layer does not affect the gate as gate will not be linked to the rate carrying metallic route till better degree steel is manufactured.

For example, we could say antenna violation is in M2. This manner that M2 has sufficient area to accumulate huge charge that induces high electron voltage to break the gate. To solve this problem, we cut a part of M2 close to failing gate and flow the routing to M3. This makes certain that when M2 is being synthetic, it does now not get linked to gate. Connection happens only when M3 gets manufactured that is lots later in time. By then fees on Metal M2 might have leaked away.

When metallic jumper isn't feasible to enforce (probably because of routing congestion or violation occurring in top most layer) we attempt to restore it with the aid of placing antenna diode closed to gate failing antenna. Antenna diode offer electric course for safe conduction of collected expenses to the substrate. Antenna diode is a reversed biased diode but acts like resistor throughout manufactured process (CMP) because of high temperature environment.

Question 7. How Do You Reduce Power Dissipation Using High Vt And Low Vt On Your Design?

Answer :

Use HVT cells for timing paths having +ve slacks.
Use LVT cells for timing paths having -ve slacks.
 HVT cells have a larger delay but much less leakage. +ve slack in a layout isn't always beneficial as having only some paths working faster will not help normal layout. We are good if the slack is 0. In such cases give up the slack by way of the usage of HVT cells however advantage on electricity dissipation.

 LVT cells are very rapid but very leaky. Limit using LVT cells to simplest the ones paths that have difficulty in last time.

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Question eight. What Is Electromigration And How To Fix It?

Answer :

Electromigration (EM) seek advice from the phenomenon of motion of metallic atoms because of momentum transfer from accomplishing electrons to steel atoms. Current conduction over a period of time in a metal path causes opens or shorts due to EM impact. EM effect can't be avoided.

 In order to reduce its effect, we use wider wires so that despite EM effect cord stays wide sufficient to behavior over the life of the IC.

Question 9. What Are The Various Statistics Available In Ir Drop Reports?

Answer :

IR drop info for VDD/ VSS.
Maximum present day thru VDD/VSS.
Number of contemporary sources for VDD/VSS.
Utilization of metallic layers used.
EM facts for sign and through.
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Question 10. What Is The Importance Of Ir Drop Analysis?

Answer :

IR drop determines the level of voltage on the pins of fashionable cells. Value of proper IR drop can be determined at the start of the project and it's miles one of the factors used to determine the derate fee.

 If the cost of IR drop is more than the suitable price, it calls to exchange the derate value. Without this modification, timing calculation will become optimistic. For example setup slack calculated with the aid of the tool is much less than the fact.

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Question 11. In Which Field Are You Interested?

Answer :

Answer to this question depends on your interest, expertise and to the requirement for that you have been interviewed.
Well..The candidate gave answer: Low power layout
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Question 12. Can You Talk About Low Power Techniques? How Low Power And Latest 90nm/65nm Technologies Are Related?

Answer :

Refer here and browse for distinctive low energy strategies.

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Question thirteen. Do You Know About Input Vector Controlled Method Of Leakage Reduction?

Answer :

Leakage cutting-edge of a gate is dependant on its inputs additionally. Hence discover the set of inputs which gives least leakage. By applyig this minimal leakage vector to a circuit it's miles feasible to lower the leakage modern of the circuit whilst it is within the standby mode. This method is referred to as enter vector controlled technique of leakage reduction.

Question 14. How Can You Reduce Dynamic Power?

Answer :

Reduce switching hobby through designing appropriate RTL
Clock gating
Architectural upgrades
Reduce deliver voltage
Use multiple voltage domain names-Multi vdd
Question 15. What Are The Vectors Of Dynamic Power?

Answer :

Voltage and Current

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Question sixteen. How Will You Do Power Planning?

Answer :

Refer here for electricity making plans.

Question 17. If You Have Both Ir Drop And Congestion How Will You Fix It?

Answer :

Spread macros
Spread preferred cells
Increase strap width
Increase number of straps
Use right blockage
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Question 18. Is Increasing Power Line Width And Providing More Number Of Straps Are The Only Solution To Ir Drop?

Answer :

Spread macros
Spread standard cells
Use right blockage
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Question 19. In A Reg To Reg Path If You Have Setup Problem Where Will You Insert Buffer-near To Launching Flop Or Capture Flop? Why?

Answer :

(buffers are inserted for solving fanout voilations and as a result they lessen setup voilation; otherwise we try to restore setup voilation with the sizing of cells; now just anticipate that you have to insert buffer !)
Near to seize course.
Because there may be other paths passing through or originating from the flop nearer to lauch flop. Hence buffer insertion may have an effect on other paths also. It may additionally enhance all those paths or degarde. If all those paths have voilation then you may insert buffer nearer to launch flop provided it improves slack.
Question 20. How Will You Decide Best Floor Plan?

Answer :

Refer right here for floor making plans.

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Question 21. What Is The Most Challenging Task You Handled? What Is The Most Challenging Job In P&r Flow?

Answer :

It can be strength making plans- because you determined more IR drop
It can be low strength goal-because you had extra dynamic and leakage energy
It can be macro placement-as it had extra reference to standard cells or macros
It may be CTS-because you needed to deal with more than one clocks and clock domain crossings
It may be timing-due to the fact sizing cells in ECO drift is not assembly timing
It can be library training-because you found some inconsistancy in libraries.
It may be DRC-because you confronted thousands of voilations
Question 22. How Will You Synthesize Clock Tree?

Answer :

Single clock-normal synthesis and optimization
Multiple clocks-Synthesis each clock seperately
Multiple clocks with domain crossing-Synthesis each clock seperately and stability the skew
Question 23. How Many Clocks Were There In This Project?

Answer :

It is particular for your challenge
More the clocks greater hard
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Question 24. How Did You Handle All Those Clocks?

Answer :

Multiple clocks-->synthesize separately-->stability the skew-->optimize the clock tree
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Question 25. Are They Come From Separate External Resources Or Pll?

Answer :

If it's miles from separate clock assets (i.E.Asynchronous; from different pads or pins) then balancing skew among these clock sources will become difficult.
If it's far from PLL (i.E.Synchronous) then skew balancing is relatively smooth.
Question 26. Why Buffers Are Used In Clock Tree?

Answer :

To stability skew (i.E. Flop to flop put off)

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Question 27. What Is Cross Talk?

Answer :

Switching of the sign in one internet can interfere neigbouring net because of cross coupling capacitance.This affect is called cros talk. Cross communicate can also lead setup or hold voilation.

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Question 28. How Can You Avoid Cross Talk?

Answer :

Double spacing=>greater spacing=>much less capacitance=>much less go speak
Multiple vias=>much less resistance=>much less RC put off
Shielding=> constant pass coupling capacitance =>recognised fee of crosstalk
Buffer insertion=>raise the sufferer power
Question 29. How Shielding Avoids Crosstalk Problem? What Exactly Happens There?

Answer :

High frequency noise (or glitch)is coupled to VSS (or VDD) seeing that shilded layers are related to either VDD or VSS.
Coupling capacitance stays steady with VDD or VSS.
Question 30. How Spacing Helps In Reducing Crosstalk Noise?

Answer :

width is extra=>greater spacing between  conductors=>go coupling capacitance is less=>much less cross talk

Question 31. Why Double Spacing And Multiple Vias Are Used Related To Clock?

Answer :

Why clock.-- because it's miles the only sign which chages it country regularly and greater as compared to some other sign. If another signal switches speedy then also we will use double space.
Double spacing=>width is extra=>capacitance is less=>much less move communicate
Multiple vias=>resistance in parellel=>much less resistance=>less RC delay
Question 32. How Buffer Can Be Used In Victim To Avoid Crosstalk?

Answer :

Buffer boom victims sign energy; buffers damage the internet period=>victims are more tolerant to coupled signal from aggressor.




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