Interview Questions.

Question 1. What Are Design Rule Check (drc) And Layout Vs Schematic (lvs) ?

Answer :

Design Rule Check (DRC) and Layout Vs Schematic (LVS) are verification methods. Reliable tool fabrication at modern-day deep submicrometre (0.Thirteen µm and underneath) requires strict observance of transistor spacing, steel layer thickness, and electricity density regulations. DRC exhaustively compares the physical netlist against a hard and fast of "foundry layout rules" (from the foundry operator), then flags any observed violations. LVS is a process that confirms that the format has the identical structure because the associated schematic; that is generally the final step within the layout process. The LVS device takes as an input a schematic diagram and the extracted view from a format. It then generates a netlist from every one and compares them. Nodes, ports, and device sizing are all as compared. If they're the equal, LVS passes and the dressmaker can maintain.

Note: LVS has a tendency to keep in mind transistor palms to be similar to an additional-huge transistor. For example, four transistors in parallel (each 1 um huge), a 4-finger 1 um transistor, and a four um transistor are all seen as the identical by means of the LVS tool. Functionality of .Lib files will be taken from spice fashions and brought as an characteristic to the .Lib document.

Question 2. What Is Antenna Effect?

Answer :

The antenna effect, more formally plasma triggered gate oxide harm, is an efffect that may doubtlessly cause yield and reliability troubles at some point of the manufacture of MOS incorporated circuits. Fabs typically deliver antenna rules, which are rules that need to be obeyed to keep away from this problem. A violation of such guidelines is referred to as an antenna violation. The word antenna is incredibly of a misnomer in this context—the trouble is really the collection of rate, no longer the normal that means of antenna, that's a device for changing electromagnetic fields to/from electric currents. Occasionally the word antenna effect is used this context[6] however this is much less common for the reason that there are numerous results[7] and the phrase does not make clear which is supposed. 

Web Designing Interview Questions
Question three. What Are Steps Involved In Semiconductor Device Fabrication?

Answer :

This is a list of processing techniques which might be hired severa instances in a cutting-edge electronic tool and do now not always mean a particular order. 

Wafer processing 
Wet cleans 
Photolithography 
Ion implantation (wherein dopants are embedded in the wafer growing areas of elevated (or reduced) conductivity) 
Dry etching 
Wet etching 
Plasma ashing 
Thermal treatments 
Rapid thermal anneal 
Furnace anneals 
Thermal oxidation 
Chemical vapor deposition (CVD) 
Physical vapor deposition (PVD) 
Molecular beam epitaxy (MBE) 
Electrochemical Deposition (ECD). See Electroplating 
Chemical-mechanical planarization (CMP) 
Wafer testing (where the electrical performance is demonstrated) 
Wafer backgrinding (to lessen the thickness of the wafer so the resulting chip may be positioned into a skinny tool like a smartcard or PCMCIA card.) 
Die practise 
Wafer mounting 
Die cutting 
IC packaging 
Die attachment 
IC Bonding 
Wire bonding 
Flip chip 
Tab bonding 
IC encapsulation 
Baking 
Plating 
Lasermarking 
Trim and shape 
IC checking out 
Question 4. What Is Clock Distribution Network?

Answer :

In a synchronous digital machine, the clock signal is used to outline a time reference for the motion of facts within that gadget. The clock distribution community distributes the clock sign(s) from a not unusual point to all of the elements that want it. Since this characteristic is critical to the operation of a synchronous machine, plenty interest has been given to the characteristics of those clock indicators and the electrical networks used of their distribution. Clock alerts are regularly seemed as simple manage alerts; however, those signals have a few very special traits and attributes.

Clock indicators are generally loaded with the greatest fanout, journey over the greatest distances, and function at the highest speeds of any sign, both control or facts, inside the whole synchronous system. Since the records indicators are supplied with a temporal reference by using the clock signals, the clock waveforms should be in particular clean and sharp. Furthermore, those clock indicators are particularly tormented by generation scaling (see Moore's regulation), in that lengthy international interconnect traces emerge as notably greater resistive as line dimensions are reduced. This expanded line resistance is one of the number one motives for the growing significance of clock distribution on synchronous performance. Finally, the control of any variations and uncertainty in the arrival instances of the clock alerts can significantly restriction the maximum overall performance of the entire gadget and create catastrophic race conditions wherein an incorrect data signal might also latch within a check in. The clock distribution community regularly takes a huge fraction of the electricity ate up by means of a chip. Furthermore, huge energy may be wasted in transitions inside blocks, even when their output is not needed. These observations have result in a energy saving approach known as clock gating, which involves including common sense gates to the clock distribution tree, so portions of the tree can be grew to become off when not wished.

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Question five. What Is Clock Gating?

Answer :

Clock gating is one of the power-saving strategies used on many synchronous circuits consisting of the Pentium four processor. To keep electricity, clock gating refers to adding additional good judgment to a circuit to prune the clock tree, thus disabling portions of the circuitry where turn flops do not exchange nation. Although asynchronous circuits through definition do now not have a "clock", the term "best clock gating" is used to demonstrate how diverse clock gating techniques are genuinely approximations of the records-established behavior exhibited via asynchronous circuitry, and that because the granularity on which you gate the clock of a synchronous circuit processes zero, the strength intake of that circuit techniques that of an asynchronous circuit.

System Verilog Interview Questions
Question 6. What Is Netlist ?

Answer :

Netlists are connectivity statistics and offer not anything extra than instances, nets, and possibly some attributes. If they explicit tons greater than this, they may be usually taken into consideration to be a hardware description language which include Verilog, VHDL, or someone of numerous specific languages designed for enter to simulators. 
Most netlists either contain or check with descriptions of the elements or devices used. Each time a element is used in a netlist, this is referred to as an "example." Thus, each example has a "master", or "definition". These definitions will generally list the connections that can be made to that type of device, and a few basic houses of that device. These connection factors are called "ports" or "pins", among several other names. 
An "instance" may be anything from a vacuum cleaner, microwave oven, or mild bulb, to a resistor, capacitor, or included circuit chip. 
Instances have "ports". In the case of a vacuum purifier, these ports would be the three steel prongs within the plug. Each port has a name, and in continuing the vacuum cleaner example, they is probably "Neutral", "Live" and "Ground". Usually, each example will have a unique call, so that if you have  instances of vacuum cleaners, one might be "vac1" and the alternative "vac2". Besides their names, they may otherwise be identical. 
Nets are the "wires" that join things together within the circuit. There may also or might not be any special attributes related to the nets in a design, depending on the specific language the netlist is written in, and that language's features. 
Instance primarily based netlists usually offer a listing of the instances used in a design. Along with every instance, either an ordered listing of internet names are furnished, or a list of pairs provided, of an instance port name, in conjunction with the internet name to which that port is connected. In this type of description, the list of nets may be collected from the connection lists, and there's no place to partner precise attributes with the nets themselves. SPICE is perhaps the maximum famous of instance-based netlists. 
Net-based netlists normally describe all the instances and their attributes, then describe every internet, and say which port they're related on every example. This lets in for attributes to be associated with nets. EDIF is probably the maximum famous of the net-primarily based netlists.
Question 7. What Physical Timing Closure?

Answer :

Physical timing closure is the method by using which an FPGA or a VLSI design with a bodily illustration is modified to satisfy its timing requirements. Most of the modifications are handled by way of EDA gear based totally on directives given through a designer. The time period is also sometimes used as a characteristic, that's ascribed to an EDA device, when it provides most of the features required on this process. Physical timing closure have become more essential with submicrometre technology, as more and more steps of the layout waft needed to be made timing-conscious. Previously handiest good judgment synthesis needed to satisfy timing requirements. With present deep submicrometre technologies it's miles unthinkable to perform any of the layout steps of placement, clock-tree synthesis and routing with out timing constraints. Logic synthesis with those technology is turning into less critical. It continues to be required, because it affords the initial netlist of gates for the location step, but the timing requirements do now not want to be strictly glad any greater. When a bodily representation of the circuit is available, the changes required to gain timing closure are achieved by way of the usage of more accurate estimations of the delays.

VLSI Interview Questions
Question eight. What Physical Verification?

Answer :

Physical verification of the design, entails DRC(Design rule test), LVS(Layout versus schematic) Check, XOR Checks, ERC (Electrical Rule Check) and Antenna Checks.

XOR Check: This step entails evaluating  layout databases/GDS with the aid of XOR operation of the layout geometries. This take a look at effects a database which has all of the mismatching geometries in each the layouts. This check is usually run after a metallic spin, wherein in the re-spin database/GDS is as compared with the formerly taped out database/GDS.

Antenna Check: Antenna tests are used to limit the harm of the thin gate oxide for the duration of the producing procedure due to price accumulation at the interconnect layers (steel, polysilicon) in the course of positive fabrication steps like Plasma etching, which creates noticeably ionized count number to etch. The antenna basically is a metallic interconnect, i.E., a conductor like polysilicon or metallic, that isn't electrically related to silicon or grounded, during the processing steps of the wafer. If the relationship to silicon does no longer exist, charges can also building up at the interconnect to the point at which rapid discharge does take area and permanent bodily harm outcomes to thin transistor gate oxide. This speedy and negative phenomenon is called the antenna effect. The Antenna ratio is defined as the ratio between the physical location of the conductors making up the antenna to the entire gate oxide location to which the antenna is electrically connected.

ERC (Electrical rule test): ERC (Electrical rule take a look at) includes checking a layout for all properly and substrate regions for correct contacts and spacings thereby ensuring accurate strength and ground connections. ERC steps can also contain assessments for unconnected inputs or shorted outputs.

Question 9. What Is Stuck-at Fault?

Answer :

A Stuck-at fault is a selected fault version used by fault simulators and Automatic test sample technology (ATPG) equipment to mimic a production illness within an integrated circuit. Individual alerts and pins are assumed to be stuck at Logical '1', 'zero' and 'X'. For instance, an output is tied to a logical 1 kingdom throughout take a look at era to guarantee that a production disorder with that kind of behavior may be found with a selected check sample. Likewise the output might be tied to a logical zero to model the behavior of a defective circuit that cannot switch its output pin. 

FPGA Interview Questions
Question 10. What Is Different Logic Family?

Answer :

Listed right here in hard chronological order of creation along with their usual abbreviations of Logic circle of relatives:

Diode good judgment (DL)
Direct-coupled transistor good judgment (DCTL)
Complementary transistor logic (CTL)
Resistor-transistor good judgment (RTL)
Resistor-capacitor transistor logic (RCTL)
Diode-transistor good judgment (DTL)
Emitter coupled logic (ECL) also known as Current-mode good judgment (CML)
Transistor-transistor good judgment (TTL) and versions
P-type Metal Oxide Semiconductor logic (PMOS)
N-type Metal Oxide Semiconductor logic (NMOS)
Complementary Metal-Oxide Semiconductor good judgment (CMOS)
Bipolar Complementary Metal-Oxide Semiconductor common sense (BiCMOS)
Integrated Injection Logic (I2L)
Question 11. What Is Different Types Of Ic Packaging ?

Answer :

IC are packaged in many sorts they may be:

BGA1
BGA2
Ball grid array
CPGA
Ceramic ball grid array
Cerquad
DIP-eight
Die attachment
Dual Flat No Lead
Dual in-line bundle
Flat p.C.
Flip chip
Flip-chip pin grid array
HVQFN
LQFP
Land grid array
Leadless chip provider
Low insertion force
Micro FCBGA
Micro Leadframe Package
MicroLeadFrame
Mini-Cartridge
Multi-Chip Module
OPGA
PQFP
Package on bundle
Pin grid array
Plastic leaded chip service
QFN
QFP
Quadruple in-line package deal
ROM cartridge
Shrink Small-Outline Package
ingle in-line package
Small-Outline Integrated Circuit
Staggered Pin Grid Array
Surface-mount technology
TO220
TO3
TO92
TQFP
TSSOP
Thin small-define package deal
Through-hollow generation
UICC
Zig-zag in-line package deal
Universal Verification Methodology (UVM) Interview Questions
Question 12. What Is Substrate Coupling?

Answer :

In an incorporated circuit, a signal can couple from one node to some other thru the substrate. This phenomenon is called substrate coupling or substrate noise coupling.

The push for decreased fee, extra compact circuit forums, and added consumer capabilities has supplied incentives for the inclusion of analog features on in most cases virtual MOS included circuits (ICs) forming combined-sign ICs. In those structures, the rate of virtual circuits is constantly increasing, chips are getting greater densely packed, interconnect layers are added, and analog decision is multiplied. In addition, recent growth in wi-fi packages and its growing marketplace are introducing a brand new set of competitive design dreams for knowing mixed-signal structures. Here, the fashion designer integrates radio frequency (RF) analog and base band digital circuitry on a unmarried chip. The goal is to make unmarried-chip radio frequency incorporated circuits (RFICs) on silicon, wherein all the blocks are fabricated on the same chip. One of the benefits of this integration is low power dissipation for portability due to a reduction within the range of bundle pins and related bond wire capacitance. Another cause that an included answer offers decrease energy consumption is that routing excessive-frequency indicators off-chip often calls for a 50O impedance in shape, that may bring about higher power dissipation. Other blessings include progressed excessive-frequency overall performance due to reduced package deal interconnect parasitics, better device reliability, smaller bundle remember, smaller package deal interconnect parasitics, and higher integration of RF components with VLSI-well matched virtual circuits. In fact, the unmarried-chip transceiver is now a reality.

Web Designing Interview Questions
Question 13. What Is Latchup ?

Answer :

A latchup is the inadvertent advent of a low-impedance course among the energy deliver rails of an digital element, triggering a parasitic shape, which then acts as a quick circuit, disrupting right functioning of the component and probable even main to its destruction due to overcurrent. A electricity cycle is required to accurate this example. The parasitic shape is usually equal to a thyristor (or SCR), a PNPN structure which acts as a PNP and an NPN transistor stacked next to every other. During a latchup whilst one of the transistors is undertaking, the opposite one begins conducting too. They both keep each other in saturation for so long as the structure is forward-biased and a few modern-day flows through it - which typically way until a power-down. The SCR parasitic structure is fashioned as a part of the totem-pole PMOS and NMOS transistor pair at the output drivers of the gates.