Interview Questions.

Top 100+ Amba Ahb Interview Questions And Answers

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Top 100+ Amba Ahb Interview Questions And Answers

Question 1. When Should A Master Assert And Deassert The Block Signal For A Locked Transfer?

Answer :

The GLOCK sign should be asserted as a minimum one cycle earlier than the start of the deal with phase of a locked switch. This is required so that the arbiter can pattern the HLOCK signal as excessive on the start of the address phase.

The grasp must deassert the HLOCK sign whilst the address segment of the remaining switch within the locked collection has began.

Question 2. Can An Arbiter Be Designed To Always Allow Bursts To Complete?

Answer :

A SPLIT, RETRY or ERROR response from a slave can usually motive a burst to be early terminated. This is outwith the manipulate of the Arbiter and so must be supported.

Undefined duration INCR bursts can not have their quit point anticipated, so there's no efficient way that an Arbiter design can permit the burst to complete before granting another grasp. INCR bursts must be arbitrated ona cycle by using cycle foundation.

Defined period INCRx and WRAPx bursts may have their beats counted, and so allowed to finish through the Arbiter. However because of the AHB arbitration synchronous timing, there may be no way to avoid likely terminating a burst straight away after the primary transfer of the burst has been indicated.

The Arbiter simplest knows that a defined period burst is in progress by using sampling the HBURST bus. However the first point at which HBURST can be sampled is after the first clock cycle of the primary burst beat, via which time the Arbiter may additionally already have determined to supply any other master and will have changed the HGRANT outputs hence. Only a combinatorial route from HBURST to HGRANT might allow the burst to be detected in time to avoid early termination in this state of affairs, but combinatorial paths within the AHB bus aren't allowed.

Python Interview Questions
Question 3. Why Is Haddr Sometimes Shown As An Input To The Arbiter?

Answer :

The address bus, HADDR, is not required as an input to the arbiter however in some system designs it may be beneficial to apply the cope with bus to determine a great factor to trade over between bus masters. For example, the arbiter could be designed to trade bus ownership when a burst of transfers reaches a quad phrase boundary.

Question four. When Can The Hgrant Signal Change?

Answer :

The GRANT sign can exchange in any cycle and the subsequent cases are feasible:

It is possible that the HGRANT signal can be asserted after which eliminated earlier than the modern-day transfer completes. This is suitable due to the fact the HGRANT signal is only sampled by using masters whilst HREADY is excessive.
A grasp may be granted the bus with out inquiring for it.
The above factor additionally method that it's miles feasible to be granted the bus inside the identical cycle that it's miles asked. This can occur if the master is coincidentally granted the bus inside the equal cycle that it requests it.
Python Tutorial
Question 5. What Is The Relationship Between The Hlock Signal And The Hmastlock Signal?

Answer :

At the start of the deal with phase of each transfer the arbiter will pattern the HLOCK sign of the master that is about to begin riding the cope with bus and if HLOCK is asserted at this factor then HMASTLOCK could be asserted through the arbiter at some stage in the cope with section of the switch.

Verilog Interview Questions
Question 6. When Should A Master Deassert Its Hbusreq Signal?

Answer :

For an undefined length burst (INCR) a grasp should keep its HBUSREQ sign asserted till it has started out the deal with segment of the remaining transfer within the burst. This will mean that if the penultimate transfer within the burst is zero wait nation then the grasp may be granted the bus for an additional transfer on the end of an undefined length burst.

For a defined length burst the grasp can deassert the HBUSREQ sign as soon as the grasp has been granted the bus for the first transfer. This can be accomplished because the arbiter is capable of depend the transfers in the burst and maintain the grasp granted until the burst completes.

However it is not a obligatory requirement for an Arbiter to allow a burst to complete, so the master will have to re-assert HBUSREQ if the Arbiter removes HGRANT earlier than the burst has been completed.

Question 7. When Will The Arbiter Grant Another Master After A Locked Transfer?

Answer :

The arbiter will constantly furnish the master an additional switch at the cease of a locked series, so the grasp is assured to perform one switch with the HMASTLOCK sign low on the stop of the locked sequence. This coincides with the statistics phase of the last transfer inside the locked sequence.

During this time the arbiter can exchange the HGRANT signals to a new bus master, however if the records segment of the last locked transfer gets either a SPLIT or RETRY reaction then the arbiter will drive the HGRANT alerts to make certain that both the grasp acting the locked sequence stays granted at the bus for a RETRY response, or the Dummy master is granted the bus for the SPLIT response.

PLC/Microcontrollers/Microprocessors Interview Questions
Question 8. Can A Master Deassert Hlock During A Burst?

Answer :

The AHB specification calls for that all deal with segment timed control indicators (other than HADDR and HTRANS) remain constant throughout a burst.

Although HLOCK isn't an cope with segment timed sign, it does without delay control the HMASTLOCK signal that's cope with section timed.

Therefore HLOCK ought to remain excessive at some stage in a burst, and can most effective be deasserted such that the following HMASTLOCK sign modifications after the final address segment of the burst.

Question nine. If A Master Is Currently Granted The Bus By Default, How Many Cycles Before Starting An Non-idle Transfer Does It Have To Assert Hbusreq?

Answer :

None. It can start a non IDLE transfer right away.

System Verilog Interview Questions
Question 10. Can A Master Perform Transfers Other Than Idle When The Bus Was Granted To It, But Not Requested By The Master?

Answer :

Yes. A grasp can carry out transfers aside from IDLE while it had not asked the bus. Please notice that in this example it is nonetheless recommended that the grasp asserts its request sign in order that the arbiter does now not trade possession of the bus to a lower priority master even as the transfers are in progress.

Question eleven. The Specification Recommends That Only sixteen Wait States Are Used. What Should You Do If More Than sixteen Cycles Are Needed?

Answer :

For some slaves it's far perfect to insert greater than sixteen wait states. For instance, a serial boot ROM which is handiest ever accessed at initial energy up ought to insert a larger range of wait states and it'd not have an effect on the calculation of the gadget performance and latency once gadget electricity up has been completed.

For other slaves a number of alternatives exist. A SPLIT or RETRY response will be used to suggest that the slave is not but capable of perform the requested statistics switch, or the slave might be accessed either in response to interrupts or after polling a status register, in either case indicating that the slave is now able to reply in an appropriate variety of cycles.

VHDL Interview Questions
Question 12. Why Is A Burst Not Allowed To Cross A 1 Kilobyte Boundary?

Answer :

If an AHB slave samples HSELx on the begin of a burst transaction, it is aware of it'll be decided on in the course of the burst. Also, a slave which is not decided on at the begin of a burst will understand that it'll now not turn out to be selected until a brand new burst is began.

1 kilobyte is the smallest vicinity an AHB slave may additionally occupy within the memory map.

Therefore, if a burst did cross a 1 kilobyte boundary, the get entry to should start having access to one slave at the beginning of the burst after which switch to any other on the boundary, which have to not show up for the above purpose.

The 1 kilobyte boundary has been selected as it's miles huge enough to permit reasonable duration bursts, but small sufficient that peripherals may be aligned to the 1 kilobyte boundary with out the use of up an excessive amount of of the to be had memory map.

Python Interview Questions
Question thirteen. Can An Ahb Master Be Connected Directly To An Ahb Slave?

Answer :

Any slave which does not use SPLIT responses may be related without delay to an AHB grasp. If the slave does use SPLIT responses then a simplified model of the arbiter is likewise required.

If an AHB grasp is hooked up directly to an AHB slave it is vital to make sure that the slave drives HREADY high at some point of reset and that the pick out signal HSEL for the slave is tied permanently excessive.

Question 14. What Is The State Of The Ahb Signals During Reset?

Answer :

The specification states that during reset the bus signals should be at legitimate degrees. This virtually approach that the signals should be good judgment '0' or '1', however no longer Hi-Z. The actual good judgment tiers pushed are left up to the fashion designer. HTRANS is the most effective sign precise during reset, with a mandatory price of IDLE.

It is vital that ALREADY is high at some stage in reset. If all slaves in the machine drive HARDY excessive at some stage in reset then this could make sure that that is the case. However, if slaves are used which do no longer pressure HREADY high during reset it need to be ensured that a slave which does power HREADY high is chosen at reset.

Question 15. Can A Busy Transfer Occur At The End Of A Burst?

Answer :

A BUSY transfer can only occur on the quit of an undefined length burst (INCR). A BUSY transfer can not arise at the quit of a set duration burst (SINGLE, INCR4, WRAP4, INCR8, WRAP8, INCR16, WRAP16).

Ethernet Interview Questions
Question 16. What Is A Default Slave?

Answer :

If the memory map of a machine does not define the overall 4 gigabyte cope with area then a default slave is required, which is chosen whilst an get right of entry to is attempted to the empty regions of the reminiscence map. The default slave have to use an OKAY reaction for IDLE/BUSY transfers and an ERROR reaction collection for NONSEQ/SEQ transfers.

Question 17. Is A Default Slave Really Necessary?

Answer :

If the entire 4 gigabyte deal with area is defined then a default slave is not required. If, but, there are undefined areas in the reminiscence map then it's miles critical to make sure that a spurious get admission to to a non-existent deal with location will now not lock up the device. The functionality of the default slave is extraordinarily easy and it's going to often make experience to enforce this inside the decoder.

Digital Logic Design Interview Questions
Question 18. Is A Dummy Master Really Necessary?

Answer :

A dummy master is vital in any machine which has a slave which can deliver SPLIT transfer responses. The dummy master is required in order that some thing may be granted the bus if all of the different masters have acquired a SPLIT reaction.

No common sense is needed for the dummy master and it could be applied via certainly tying off the inputs to the grasp cope with/manipulate multiplexer for the dummy master function. The requirements for a dummy grasp are that HTRANS is driven to IDLE, GLOCK is driven low, and all other master outputs are pushed to felony values.

Verilog Interview Questions
Question 19. Is It Specified That Hprot, Hsize And Hwrite Remain Constant Throughout A Burst?

Answer :

Yes, the manipulate alerts need to remain constant during the length of a burst.

Question 20. What Default State Should Be Used For The Hready And Hresp Outputs From A Slave?

Answer :

It is recommended that the default price for HREADY is high and the default fee for HRESP is OKAY. This mixture ensures that the slave will reply efficaciously to IDLE transfers to the slave, even if the slave is in a few shape of energy saving mode.

8051 Microcontroller Interview Questions
Question 21. Is Hready An Input Or An Output From Slaves?

Answer :

An AHB slave must have the HREADY signal as both an enter and an output.

HREADY is required as an output from a slave so that the slave can enlarge the statistics segment of a switch.

HREADY is also required as an input in order that the slave can decide when the previously selected slave has completed its final switch and the primary statistics section switch for this slave is ready to start.

Each AHB Slave should have an HREADY output sign (conventionally named HREADYOUT) which is connected to the Slave-to-Master Multiplexer. The output of this multiplexer is the global HREADY sign that is routed to all masters on the AHB and is also fed lower back to all slaves as the HREADY input.

Question 22. How Many Masters Can There Be In An Ahb System?

Answer :

The AHB specification caters for up to 16 masters. However, bearing in mind a dummy bus master method the maximum range of actual bus masters is genuinely 15. By conference bus grasp quantity zero is allotted to the dummy bus grasp.

Question 23. Can A Master Change The Address/manage Signals During A Waited Transfer?

Answer :

Yes. If the cope with/manage indicators are indicating an IDLE transfer then the grasp can change to a actual switch (NONSEQ) whilst HREADY is low.

However, if a master is indicating a actual switch (NONSEQ or SEQ) then it cannot cancel this at some point of a waited transfer except it gets a SPLIT, RETRY or ERROR response.

Advanced C++ Interview Questions
Question 24. When A Master Rebuilds A Burst Which Has Been Terminated Early Are There Any Limitations On How It Rebuilds The Burst?

Answer :

The best dilemma is that the master makes use of felony burst combinations to rebuild the burst. For example, if a grasp turned into acting an 8 beat burst, however had handiest completed three transfers before dropping control of the bus, then the ultimate 5 transfers might be completed both by using the usage of a 1 beat SINGLE burst accompanied via a 4 beat INCR burst, or it is able to be completed the usage of a 5 beat undefined length INCR burst.

For simplicity it's far encouraged that masters use INCR bursts to rebuild the ultimate transfers.

PLC/Microcontrollers/Microprocessors Interview Questions
Question 25. What Is The Recommended Default Value For Hprot?

Answer :

Many bus masters will not be able to generate correct safety data and for these bus masters it is endorsed that the HPROT encoding indicates, Non-cacheable, Non-bufferable, Privileged, Data Accesses which corresponds to HPROT[3:0] = four'b0011.

Question 26. Do All Slaves Have To Support The Busy Transfer Type?

Answer :

Yes. All slaves have to help the BUSY switch type to make certain they may be well suited with any bus master.

FPGA Interview Questions
Question 27. What System Support Is Required If A Slave Can Be Powered Down Or Have Its Clock Stopped?

Answer :

If a slave get right of entry to is tried even as that slave is in a power down kingdom or has had its clock stopped, you need to make certain that an access will purpose the energy/clock to be restored, in any other case configure the AHB decoder as much as redirect the sort of accesses to the dummy slave so that the machine does now not hold forever when an get admission to to the tool is made whilst it's far disabled.

Redirecting the get admission to on this way will make certain that random "IDLE" addresses are dealt with with the HREADY excessive and HRESP=OKAY default response, but actual accesses (NONSEQ or SEQ) could be detected with an ERROR reaction.

System Verilog Interview Questions
Question 28. When Can Early Burst Termination Occur?

Answer :

Bursts may be early terminated both due to the Arbiter removing the HGRANT to a master part way thru a burst, or after a slave returns a non-OKAY reaction to any beat of a burst. Note however that a grasp cannot decide to terminate a defined length burst until precipitated to accomplish that by way of the Arbiter or Slave responses.

All AHB Masters, Slaves and Arbiters should be designed to assist Early Burst Termination.

Question 29. Does The Address Have To Be Aligned, Even For Idle Transfers?

Answer :

Yes. The deal with must be aligned in keeping with the switch length (HSIZE) even for IDLE transfers. This will save you spurious warnings from bus monitors used throughout simulation.

ASIC Interview Questions
Question 30. What Is The Difference Between A Dummy Bus Master And A Default Bus Master?

Answer :

The time period default bus grasp is used to explain the master that is granted whilst none of the masters in the machine are requesting get admission to to the bus. Usually the bus grasp which is maximum probably to request the bus is made the default grasp.

The dummy bus grasp is a master which most effective plays IDLE transfers. It is required in a system so the arbiter can furnish a grasp that's guaranteed no longer to carry out any actual transfers. The two cases whilst the arbiter could need to do this are while a SPLIT reaction is given to a locked transfer and while a SPLIT response is given and all other masters have already been SPLIT.

Question 31. Is It Legal For A Master To Change Haddr When A Transfer Is Extended?

Answer :

If a grasp is indicating that it wants to do a NONSEQ, SEQ or BUSY switch then it cannot alternate the address all through an extended transfer(when HREADY is low) until it receives an ERROR, RETRY or SPLIT response.

If the master is indicating that it desires to do an IDLE transfer then it may trade the address.

Question 32. Can Htrans Change Whilst Hready Is Low?

Answer :

In trendy, an AHB master have to now not trade manage indicators while HREADY is low.

However it is allowable to change HTRANS within the following conditions:

HTRANS = IDLE
The AHB master is performing internal operations and has no longer yet devoted to a bus switch. However in the course of the AHB wait states (HREADY low) the master may determine that a bus transfer is required and alternate
HTRANS on the next cycle to NONSEQ.
HTRANS = BUSY
HTRANS is being used to give the grasp time to finish internal operations, which may be absolutely impartial of HREADY (i.E. Wait states at the AHB). Therefore HTRANS can alternate on the following cycle to any criminal cost, i.E. SEQ if the burst is to maintain, IDLE if the burst has completed, NONSEQ if a separate burst is to start.

HRESP = SPLIT/RETRY

As said inside the AHB specification, a grasp should assert IDLE on HTRANS throughout the second cycle of the 2-cycle SPLIT or RETRY slave reaction so HTRANS will alternate value from the first cycle to the second cycle of the response.
HRESP = ERROR
The grasp is permitted to alternate HTRANS in response to an ERROR response inside the identical manner as in reaction to a SPLIT/RETRY response and cancel any further beats within the modern-day burst (although HBURST is indicating a described-period burst). In this example HTRANS adjustments to IDLE on the second one cycle of the response. Alternatively, the master is authorized to hold with the present day transfers

Universal Verification Methodology (UVM) Interview Questions
Question 33. What Are The Different Bursts Used For?

Answer :

Typically a grasp could use wrapping bursts for cache line fills in which the grasp desires to get entry to the information it calls for first and then it completes the burst to fetch the last information it calls for for the cache line fill.

Incrementing bursts are used by masters, which includes DMA controllers, which are filling a buffer in memory which may not be aligned to a specific address boundary.

VHDL Interview Questions
Question 34. How Should Ahb To Apb Bridges Handle Accesses That Are Not 32-bits?

Answer :

The bridge ought to virtually pass the complete 32-bit records bus through the bridge. Please observe that when transfers much less than 32-bits are carried out to an APB slave it's far critical to make certain that the peripheral is positioned on the perfect bits of the APB records bus.

Question 35. What Value Should Be Used For Htrans When An Ahb Master Gets A Retry Response From A Slave In The Middle Of Burst?

Answer :

Whenever a switch is restarted it ought to use HTRANS set to NONSEQ and it may additionally be vital to alter the HBURST statistics (usually just to suggest INCR).

Question 36. What Address Should Be On The Bus During The Idle Cycle After A Split Or Retry?

Answer :

It does no longer be counted what address is driven onto the bus throughout this cycle.

The slave selected by using the driven address ought to now not take any movement and ought to reply with a zero wait state OKAY reaction.

In many cases it'll be less complicated for the grasp to depart the deal with unaltered for the duration of this cycle, so that it stays at the deal with of the next transfer that the grasp needs to perform and best inside the following cycle does the master return the address to that of the switch that have to be repeated due to the SPLIT or RETRY reaction.

In some designs it could be feasible for the master to go back the deal with to that required to copy the previous switch all through the IDLE cycle and this behaviour is likewise perfectly ideal.

Ethernet Interview Questions
Question 37. Do All Masters Have To Support Split And Retry?

Answer :

Yes. All masters must guide SPLIT and RETRY responses to make certain they may be well matched with any bus slave. A master will take care of each SPLIT and RETRY responses in an identical manner.

Question 38. Can A Split Or Retry Response Be Given At Any Point During A Burst?

Answer :

Yes. A SPLIT, RETRY or ERROR reaction may be given via a slave to any transfer all through a burst. The slave isn't always restricted to most effective giving those responses to the first switch.

Question 39. Will A Master Always Lose The Bus After A Split Response?

Answer :

Yes. A slave ought to not assert the applicable bit of the SPLIT bus within the same cycle that it gives the SPLIT response and therefore the master will continually lose the bus.

Question 40. Can A Slave Assert Hsplitx In The Same Cycle That It Gives A Split Response?

Answer :

No. The specification calls for that HSPLITx can most effective be asserted after the slave has given a SPLIT reaction.

Digital Logic Design Interview Questions
Question 41. Do All Slaves Have To Support The Split And Retry Responses?

Answer :

No. A slave is simplest required to help the reaction types that it needs to apply. For instance, a easy on-chip memory block which can respond to all transfers in only a few wait states does now not need to use either the SPLIT or RETRY responses.

Question forty two. Can A Slave Use Both Split And Retry Responses?

Answer :

Normally a slave will not use each the SPLIT and RETRY responses. The SPLIT response have to be utilized by any slave that may be accessed by many one of a kind masters on the equal time. The RETRY response is supposed to be used by peripherals which are most effective accessed by means of one bus grasp.

8051 Microcontroller Interview Questions
Question forty three. What Is The Difference Between Split And Retry Responses?

Answer :

Both the Split and Retry responses are used by slaves which require a large quantity of cycles to complete a transfer. These responses allow a facts phase transfer to appear finished to avoid stalling the bus, but at the same time suggest that the switch should be re-attempted whilst the master is next granted the bus.

The difference between them is that a SPLIT response tells the Arbiter to provide precedence to all other masters until the SPLIT transfer may be completed (correctly ignoring all further requests from this master till the SPLIT slave indicates it is able to whole the SPLIT switch), whereas the RETRY response best tells the Arbiter to present priority to better priority masters.

A SPLIT response is more complicated to implement than a RETRY, but has the benefit that it permits the maximum performance to be product of the bus bandwidth.

The grasp behaviour is equal to both SPLIT and RETRY responses, the master has to cancel the following get entry to and re-try the contemporary failed get right of entry to.




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