Interview Questions.

Q1. Flow of Complete PCB design.

Ans:

 Library creation

Board outline and mechanicals

Importing netlist

Design Rule settings

Component Placement

 Rounting

 Split plans

 Silkscreen and Assembly settings

Gerber Settings

Q2. What are the inputs you want to layout a PCB?

Ans:

We want schematic,bom and netlist(a few pcb engineer generates netlist) from Hardware facet and Board mechanicals from consumer i.E, board define,mounting holes and so forth.

And every other critical factor that we want is PCB stackup it's far based totally on complexity of the board as an example if we're the use of fpga first we ought to know variety of sign layers want for fpga signal breakout.

Q3. How to create footprint?            

Ans: Footprint go with the flow:

Padstack creation

pin placement

assembly define

silkscreen define

Place sure top (we will point out height of the right here)

dfa certain top

no probe pinnacle

silk and assembly reference designator

These are the primary matters we want to create a footprint,comply with IPC standards for proper pointers.

Q4. Board mechanicals.

Ans: Draw board outline through thinking about customer requirements,area mechanical hols and worldwide fiducials.Create route keepin and location keepin areas,

Questions that can be raised from this:

length of the mechanical holes that you have used on your layout and clearances that you have given to these.

What are fiducials and use of these fiducials and brands and differences between them.

Fiducial placement and clearances.

What are the clearances you have got given from board outline to course and place keepin.

Q5. What are the mistakes you acquire at the same time as importing netlist?

Ans: 

pcb footprint now not determined.

Pins mismatch between image and footprint etc.
 

Q6. How do you define layout policies?

Ans: Design guidelines are nothing but growing tracewidth, spacing, vias barriers. Generally we get trace width and spacing details from stackup.

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Q7. How do area additives?

Ans: Place major components first i.E connectors, BGAs, mejor ICs then place different sections.

How do you location connectors?

First check climate i.E right perspective or directly.If it's far right perspective place at edge of the board and bear in mind if there any recommendations from patron. 

Q8. How do you plan routing and what are the parameters you recollect while routing?

Ans: Placement routing performs  essential  roles in pcb design, best of the board relies upon on placement and routing, correct placement and routing can lessen your board fabrication value also.

Place additives through considering routing strategy  and observe schematic  drift as soon as your placement is achieved do fanout for all the additives, direction high velocity interfaces and complicated areas first and maintain floor reference plane for all high speed indicators and ensure that each hint has reference plane and try and lessen vias on signals vias can trade hint function impedance.

Which PCB/CAD tools does Freedom CAD use for format?

 

Ans: Cadence Allegro: We have substantial enjoy with the Cadence Allegro device suite; we currently help versions 15 and 16. We are proud to be one of a handful of Early Adopter Program Members with Cadence.

Q9. Mentor Graphics Expedition, Power PCB (PADS) and Board Station:

Ans: We currently help WG2004, EXP 2005.1, EXP 2005.3, EXP 2007 variations of Expedition, variations 2005sp1, 2005sp2 and 2009 of PADS and Board Station versions EN2002, EN2004, BSTN2005, BSTN2006, and BSXE2006. PADS 2007 is presently underneath evaluation for destiny assist, please contact us for more records.

Valor Enterprise 3000:  This is a cornerstone process tool for Freedom CAD to guarantee manufacturability and minimum delays inside the fabrication procedure. We are a Valor Certified Design Partner.

Custom Programs: Over the past 10 years we have advanced custom applications and scripts to gain efficiencies, improve satisfactory and increase the cutting-edge layout gear.

Q10. How do you calculate the hint impedance of a PCB hint?

Ans: There are many strategies. A formula method gives a short result, even though it isn't noticeably accurate. A 2D Field solver gives extra accurate end result. The Trace impedance relies upon upon the width of the hint, separation from the floor / power aircraft, and the relative permittivity of the fabric.

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Q11. What is the difference among a blind and buried through?

Ans: Blind vias are use to attach an inner layer to either the pinnacle or bottom layer. A buried through is used for connecting  inner layers. It does no longer move both to the top or the lowest layer. A normal via ( unique from the blind and the buried through connects the top and the lowest layer and additionally passes thru the internal layers.

Do no longer prevent here. Go beforehand and draw the diagram of the blind and the buried via.

Q12. What is the usage of a decoupling capacitor?

Ans: A decoupling capacitor is used to smoothen the energy supply noise. It ought to be positioned as near the ICs for which it is supposed as viable.

Q13. What is DRC? What Kind of DRC errors you find in PCB Design?

Ans: DRC stands for Design Rule checking. A PCB have to now not have any electric failure before we tape out for the producing. Common DRC mistakes include, hint to pad violation, pad to pad violation, thing keep out violation. Additionally a PCB Design may also have high speed design rule associated constraints. This can also include, length matching constraints, differential sign duration matching constraint.

Q14. What are the stuff you must do you make certain design for compliance for EMI?

Ans: We should use not unusual mode chokes for all cables connectors. The common mode chokes ought to be located as close to the connector as feasible. The Power and ground planes should be as close to each different as possible. The High speed sign ought to confer with a floor or power aircraft and must no longer move a break up aircraft. Stitching capacitor should be used in case break up aircraft is used.

Q15. A large thermal pad is divided into four sections? What is using it?

Ans: The open region between the 4 sections lead to break out of the gases at some stage in the reflow and soldering procedure. It ends in better manufacturability.

Q16. The width of a trace is elevated ? Will its feature impedance growth of lower ?

Ans: The Capacitance consistent with unit length of the hint increases and therefore, the function impedance of the trace decreases.

Q17. Robert, what are the maximum significant problems that you are seeing in PCB designs nowadays?

Ans: It's dependent on the layout - whether it is excessive speed/low velocity, high area price/decrease area charge, a simple PCB or big backplane layout.  However, some of the obvious issues are transmission line reflection due to the capacitive load; floor bounce; crosstalk between violent aggressors (like CMOS) and sensitive victims (like ECL/PECL and analog); bypassing and strength shipping; common mode differential pair issues; and high velocity clock loading.

Q18. How speedy are the fastest forums you're seeing? How complicated in phrases of additives and pins?

Ans: Several students in my classes are designing backplanes, servers and blades that have clock frequencies up to 11GHz.  I consulted for a employer that built a backplane with sixty five BGAs having over six hundred balls each, 34 layers and over 58K solder joints. The fastest digital board (not microwave) turned into an aerospace layout strolling at 43 GHz.  Regarding components, there may be a BGA photographs processor with a clock pace of five.6 GHz that has over 3400 balls.  How might you like to reflow solder that one?

Q19. Day 1 of your seminar covers transmission strains. What are the most crucial factors you may be making?

Ans: The most sizeable aspect could be defining the cutoff situations to determine when a land trace acts like a transmission line as opposed to a lumped circuit. This will decide to a large degree the termination scheme on the way to be used to decrease mirrored image.  It is likewise critical to define pores and skin effect, dielectric loss and proximity effect.  The interesting point about proximity impact is if the spaces are just a fraction of the land width (like five to one) this will create more sign loss than pores and skin effect, dielectric and surface roughness combined.

Another problem is signal put off for microstrip and stripline.  With microstrip, the postpone isn't always the equal for naked, solder mask covering and conformal masking (encapsulation over the solder mask). I'll additionally communicate about supplying the evaluation for feature impedance and postpone expressions for microstrips, buried microstrips, striplines and differentials.

Q20. What design strategies are had to hold sign integrity beneath manage?

Ans: Excellent conversation among the EE design engineer, the PCB layout engineer, the check engineer and production engineer is essential.  Also, close coordination with the bareboard supplier and the EMS supplier is critical.  The inputs from all of those will influence the high-quality layout strategies for attaining signal integrity.  It may be very crucial to conduct digital simulation (as with Cadence Allegro SI) and EMI/EMC simulation. The extra up the front the ability trouble identity, the less debug time, the less issues at some stage in compliance trying out, and the faster the time to market.

Q21. What crosstalk problems are you seeing in high-speed designs (Day 2)?

Ans: High density board layout is very hard.  I actually have visible designs wherein 2s and 2s [2 mil-in wide land traces and spacing] are being used because of density/packaging regulations.  Interference between CMOS/TTL excessive edge fees and ECL/PECL is every other problem.  Yet another predominant situation is touchy analog circuits in near proximity to the short edge fee virtual signals.  This is wherein shield traces across the analog strains turn out to be effective.

Q22. How does crosstalk effect layer stacking?

Ans: To control crosstalk there must be a distance among the aggressor and the victim versus the gap to the reference ground aircraft or energy aircraft.  Therefore, the tradeoff in many cases is how do I minimize my stackup layers (that is a cost attention) as opposed to controlling the crosstalk, and additionally the feature impedance, which is likewise a correlation between trace width and distance to the reference aircraft (or planes as in striplines).

As every new design is launched there is typically a better clock fee with better edge charges, greater signals in step with IC bundle, and a need for better density that exacerbates crosstalk.  In my estimation this can be one of the main demanding situations for the design network, as competition and price issues will particularly have an impact on the layer stacking.

Q23. What do designers need to do to make sure ok power transport within a detailed electricity envelope (Day 3)?

Ans: In one word it's inductance.  Designers want to identify how tons inductance is inherent in the set up capacitor loop and the ESL [equivalent series inductance] of the capacitor.  The traits of the electricity and ground planes also are essential. Today cores are being produced with less than 1 mil-in of dielectric thickness.  If these are used, they'll decorate the strength shipping, however at what value?

Designers need to understand the bypassing capability in their output drivers.  The most effective way to overcome SSO [simultaneous switching output] is at the die degree.  So designers need to provide the proper dq/dt on the needed IC pin at the proper time.

Therefore, one need to recognise the maximum stage of power delivery noise allowed within the usual noise price range.  With that know-how the great approach is to offer the perfect IC die capacitance, internal aircraft capacitance, discrete capacitance and capacitor kinds (together with X2Y, Y cap, opposite electrode) to gain this intention.  Another issue, mainly as frequency will increase, is the anti/parallel resonance considerations that may require breaking up the capacitors into banks with distinctive ESRs [equivalent series resistances] and unique loop inductances.

Q24. What "excellent practices" do you advise for differential signaling and clock distribution (Day four)?

Ans: Probably the primary subject is differential unbalance as a result of the two traces now not being the identical electric length.  This reasons common mode and is the main cause differentials can fail EMI radiation.  Another attention is to assign the extra sensitive pairs as striplines. Avoid broadside layouts, that is, lead them to be aspect to edge.  Broadside layouts in many instances can render the design inoperable because of returning currents being contained on one of a kind ground planes, or probably power planes, which can purpose the receiver to peer a totally distinctive noise spectrum on its inputs.

Q25. When does EMI end up a difficulty in PCB layout, and what do designers need to realize (Day five)?

Ans: The two large concerns are radiated emissions and ESD [electro-static discharge].  All radiated emission formulation have both area rate and frequency as  of the parameters.  Therefore, most of the signal integrity rules also practice to EMI.  The main motive of radiation from circuit boards is the dimensions of the antenna loop -- this is, the pathway the contemporary takes to the burden and the course/pathway that it takes to return to the VRM module.  The extra vicinity this entails, the extra radiation.

The dressmaker must understand the ESD pulse edge rate, which in flip will define the safety tool (TVSS) or the clear out.  Another subject these days is the ever growing frequency, higher clock charges, and strength dissipation in the layout.  Designs are becoming denser with extra power dissipation.  Due to the better clock charges the apertures are decreasing in size to limit harmonic radiation, that means that the wavelengths are getting shorter.  However, with smaller apertures the layout is a whole lot much less green in permitting warmness to escape the enclosure.  This is one of the major worries in EMI mechanical compatibility design.

Q26. What will each day of the seminar cowl, and the way will Cadence equipment be confirmed?

Ans: Each day at the conclusion of the training session, Cadence engineers will exhibit examples of the lecture material.  This will provide the student with real international examples of the strategies used to design effectively.  The following presents an itinerary of the guides.

TRANSMISSION LINES (Day 1): Fundamentals of transmission strains along with stripline vs micro-strip. Cadence Demo: Pre- and submit-path SI analysis using best and lossy transmission strains.

CROSSTALK (Day 2): Stack-up optimization and ahead/reverse crosstalk. Cadence Demo: Pre- and publish-path crosstalk evaluation as well as crosstalk estimation.

POWER DELIVERY (Day three): Proper use of decoupling capacitors and figuring out strength plane resonance. Cadence Demo: Allegro PCB Power Delivery Network (PDN) analysis

DIFFERENTIAL SIGNALING (Day 4): Loosely vs. Tightly coupled differential pairs; clock distribution. Cadence Demo: Tandem and large-facet differential pair routing and evaluation.

EMI/EMC (Day five): Source, course, and receptor as well as how EMI/EMC checks are carried out. Cadence Demo: EM manipulate rule checking and EMI net analysis.

Q27. What's your maximum vital advice for customers working with high-speed digital forums? 

Ans: One could write a book in this, however to briefly country the advice: know the policies of excessive velocity design, work as a team inside the prototype design, simulate the layout, and paintings intently with the bare board vendor.