Digital Design Interview Questions and Answers
Q1. What is a multiplexer?
Ans: A multiplexer is a combinational circuit which selects one in every of many enter alerts and directs to the most effective output.
Q2. What is meant via LUT?
Ans: LUT: Look-Up Table. An n-bit look-up table may be implemented with a multiplexer whose choose lines are the inputs of the LUT and whose inputs are constants. An n-bit LUT can encode any n-enter Boolean function via modeling such capabilities as truth tables. This is a good way of encoding Boolean good judgment capabilities, and LUTs with 4-6 bits of input are in reality the important thing thing of modern FPGAs.
Q3. What is supposed via bit Binary multiplier?
Ans: Binary multiplication process: A Binary Multiplier is a digital circuit utilized in digital electronics to multiply two binary numbers and offer the end result as output. The technique used to multiply two binary numbers is just like the approach taught to high school children for multiplying decimal numbers that's based on calculating partial product, shifting them and including them together. Similar method is used to multiply binary numbers. Long multiplicand is multiplied by using zero or 1 that's plenty less complicated than decimal multiplication as product by using zero or 1 is 0 or same variety respectively. Figure 1 below shows the block diagram of a 2-bit binary multiplier. The numbers A1A0 and B1B0 are elevated collectively to provide a four-bit output P3P2P1P0. (The most product term may be 3 * three = nine, that's 1001, a 4-bit variety).
Q4. What is a ring counter?
Ans: A ring counter is a form of counter composed of a round shift sign up. The output of the closing shift sign in is fed tothe enter of the primary check in. For instance, in a 4-sign in counter, with initial sign up values of 1100, the repeatingpattern is: 1100, 0110, 0011, 1001, 1100, so on.
Q5. What are PLA and PAL? Give the differences between them.
Ans: Programmable Logic Array is a programmable tool used to put into effect combinational common sense circuits. The PLA has a hard and fast of programmable AND planes, which hyperlink to a fixed of programmable OR planes, that can then be conditionally complemented to supply an output.
PAL is programmable array good judgment, like PLA, it also has a extensive, programmable AND aircraft. Unlike a PLA, the OR plane is fixed, restricting the variety of phrases that can be ORed collectively.
Due to fixed OR aircraft PAL lets in more area, which is used for different basic logic gadgets, such as multiplexers, one of a kind-ORs, and latches. Most importantly, clocked elements, typically turn-flops, can be protected in PALs. PALs also are extremely rapid.
Q6. 16x1 mux using 4x1 muxes
Ans: Implementing sixteen:1 multiplexer with 4:1 multiplexers: A 16x1 mux may be implemented the use of 5 4x1 muxes. 4 of those multiplexers may be used as first stage to mux 4 inputs every with least extensive bits of choose lines (S0 and S1), resulting in four intermediate outputs, which, then can be muxed once more the usage of a four:1 mux. The implementation of 16x1 mux using 4x1 muxes is proven under in determine 1:
Q7. Compare and Contrast Synchronous and Asynchronous reset.
Ans: Synchronous reset common sense will synthesize to smaller turn-flops, specially if the reset is gated with the logicgenerating the d-enter. But in one of these case, the combinational common sense gate rely grows, so the overall gate countsavings might not be that huge. The clock works as a filter for small reset system faults; however, if these glitchesoccur near the energetic clock area, the Flip-flop should pass metastable. In a few designs, the reset ought to be generated bya set of internal conditions. A synchronous reset is usually recommended for those kinds of designs as it will clear out thelogic equation glitches between clock.Problem with synchronous resets is that the synthesis tool can not without problems distinguish the reset sign from any otherdata signal. Synchronous resets may also want a pulse stretcher to assure a reset pulse width extensive enough to ensurereset is gift during an lively edge of the clock, when you have a gated clock to shop power, the clock may bedisabled coincident with the statement of reset. Only an asynchronous reset will work in this case, because the resetmight be removed previous to the resumption of the clock. Designs that are pushing the restrict for information path timing, can't have enough money to have delivered gates and further internet delays within the records path because of common sense inserted to handle synchronousresets.
Q8. How can you convert a JK flip-flop to a D flip-flop?
Ans: Connect the inverted J enter to K enter.
Q9. What is the Reset fundamentals?
Ans: Purpose of reset: We see that nearly every digital tool has a reset button. Your video game has a reset button that resets the game and your unsaved progress is lost. Your laptop's reset button reboots it. Have you ever wondered why a machine (or specially a chip) has a reset? Well, the easy motive of resets is to provide a regarded initial state to the device to begin with. Another purpose is, while the device by chance is going into a few unknown nation (there may be many motives for this), the gadget constantly knows a way to get out of this and pass right into a acknowledged kingdom via putting forward a reset signal.
Reset design techniques:
Defining a reset is one of the most important selections that wishes to be taken for the best health of design. In fashionable, following things want to be saved in mind throughout figuring out reset approach:
What flops to receive reset: One of the easiest and safest techniques is to permit all of the flip-flops within the layout with a reset. However, there may be a a few registers, whose preliminary nation will no longer have any effect on the layout nation. In other phrases, it won't depend if the sign in's output is '0' or '1' while layout is going in reset state. Such registers may be saved non-resettable after an analysis. Let us problematic with the help of an example. Figure 1 suggests part of an FSM wherein two registers are feeding an AND gate. In determine 1(a), we've got decided to initialize each to 'zero' in the course of reset (with an asynchronous reset, to be defined later). However, given this scenario, if one of the turn-flops is provided with an initial nation of '0', the output of the alternative might be gated. So, we can also leave out reset on one of the flip-flops. Figure 1(b) suggests that omission of reset on one of the turn-flops does now not have any impact on country device layout.
We may not continually stumble upon such eventualities. If, rather than AND gate, we had an OR gate, we would no longer have been capable of keep one of the flip-flops uninitialized for the duration of reset. Figure 2 indicates such an example. In discern 2(b), if we put off reset from 2nd turn-flop, output of OR gate is going 'X'; as a consequence, impacting the country gadget.
Another popular state of affairs wherein we are able to pass a few registers from having a reset pin is shift registers. If the first level of a shift check in is you deliver multiple clock pulses when in reset nation, subsequent levels will get reset. If you've got four levels, you need to give at the least three clock pulses even as in reset. The identical is proven in figure beneath.
Synchronous vs asynchronous reset: There are sorts of reset statement/deassertion techniques - synchronous vs asynchronous reset. Although each of the two can be used to effective implementation of reset, every of those has its very own advantages/risks. Designer may also determine upon the favored method by way of considering the pros and cons.
Synchronous reset manner that the reset will have an effect on the kingdom of the design handiest on the energetic fringe of the clock.
Asynchronous reset resets the design asynchronously. For this motive, turn-flops have a unique pin that resets the output to '0' or '1' based upon the want.
Q10. What is a Johnson counter?
Ans: Johnson counter connects the complement of the output of the final shift sign in to its enter and circulates a streamof ones followed by using zeros around the ring. For example, in a 4-register counter, the repeating pattern is: 0000, 1000,1100, 1110, 1111, 0111, 0011, 0001, so on.
Q11. How to build an XOR gate the use of NAND gates?
Ans: We can construct a 2-input XOR gate using best 3 NAND gates. Sound interesting, isn't it? Let us see hos.
As we know, the logical equation of a 2-enter XOR gate is given as beneath:
Y = A (xor) B = (A' B + A B')
Let us take an technique where we bear in mind A and A' as extraordinary variables for now (optimizations associated with this, if any, will recollect later). Thus, the logic equation, now, becomes:
Y = (CB + A D) ----- (i)
C = A' and D = B'
De-Morgan's regulation states that
m + n = (m'n')'
Taking this under consideration,
Y = ((CB)'(AD)')' = ((A' B)' (A B')')'
Thus, Y is identical to ((A' nand B) nand (A nand B')). No in addition optimizations to the common sense seem possible to this good judgment. Figure 1 below suggests the implementation of XOR gate the usage of 2-enter NAND gates.
Q12. In a 4-bit Johnson counter How many unused states are gift?
Ans: 4-bit Johnson counter: 0000, one thousand, 1100, 1110, 1111, 0111, 0011, 0001, 0000.Eight unused states are gift.
Q13. Delay line based Time to digital converter.
Ans: A time to virtual converter is a circuit that digitizes time; i.E., it converts time into virtual wide variety. In other words, a time-to-digital converter measures the time c programming language among activities and represents that interval in the shape of a digital number.
TDCs are used in locations wherein the time c language among events needs to be determined. These occasions may additionally, for instance, be represented by using growing edges of indicators. Some packages of TDCs include time-of-flight dimension circuits and All-Digital PLLs.
Delay line based totally time-to-virtual converter: This is a completely primitive TDC and includes a postpone-line which is used to postpone the reference sign. The other signal is used to sample the kingdom of delay chain. Each level of put off chain outputs to a turn-flop or a latch that's clocked by way of the pattern sign. Thus, the output of the TDC paperwork a thermometer code as the level will show a ‘1’ if the reference signal has handed it, otherwise it will show a 0.
Q14. What are the variations among a flip-flop and a latch?
Ans: Flip-flops are area-touchy gadgets in which as latches are degree touchy gadgets.Flip-flops are immune to system faults wherein are latches are sensitive to glitches.Latches require less wide variety of gates (and therefore much less electricity) than turn-flops.Latches are faster than flip-flops.
Q15. What is the difference between Mealy and Moore FSM?
Ans: Mealy FSM makes use of best input actions, i.E. Output relies upon on enter and kingdom. The use of a Mealy FSM leads frequently to areduction of the quantity of states.Moore FSM uses most effective entry moves, i.E. Output depends handiest on the kingdom. The gain of the Moore version is asimplification of the conduct.